Patents by Inventor Eric C Palmer

Eric C Palmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Passive within via
    Patent number: 9960079
    Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Todd B. Myers, Nicholas R. Watts, Eric C. Palmer, Jui Min Lim
  • PASSIVE WITHIN VIA
    Publication number: 20130249112
    Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 26, 2013
    Inventors: Todd B. Myers, Nicolas R. Watts, Eric C. Palmer, Jui Min Lim
  • Method of embedding passive component within via
    Patent number: 8487446
    Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: July 16, 2013
    Assignee: Intel Corporation
    Inventors: Todd B Myers, Nicolas R Watts, Eric C Palmer, Jui Min Lim
  • Package on package using a bump-less build up layer (BBUL) package
    Patent number: 8093704
    Abstract: In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: January 10, 2012
    Assignee: Intel Corporation
    Inventors: Eric C. Palmer, John S. Guzek
  • METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA
    Publication number: 20110198723
    Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
    Type: Application
    Filed: April 27, 2011
    Publication date: August 18, 2011
    Inventors: Todd B. Myers, Nicholas R. Watts, Eric C. Palmer, Jui Min Lim
  • Method of embedding passive component within via
    Patent number: 7952202
    Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventors: Todd B Myers, Nicholas R. Watts, Eric C Palmer, Jui Min Lim
  • Via including multiple electrical paths
    Patent number: 7737025
    Abstract: A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Todd B Myers, Nicholas R. Watts, Eric C Palmer, Renee M Defeo, Jui Min Lim
  • PACKAGE ON PACKAGE USING A BUMP-LESS BUILD UP LAYER (BBUL) PACKAGE
    Publication number: 20090294942
    Abstract: In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented.
    Type: Application
    Filed: June 3, 2008
    Publication date: December 3, 2009
    Inventors: Eric C. Palmer, John S. Guzek
  • METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA
    Publication number: 20090057910
    Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 5, 2009
    Inventors: Todd B. Myers, Nicholas R. Watts, Eric C. Palmer, Jui Min Lim
  • Method of embedding passive component within via
    Patent number: 7275316
    Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: October 2, 2007
    Assignee: Intel Corporation
    Inventors: Todd B Myers, Nicholas R. Watts, Eric C Palmer, Jui Min Lim
  • Via including multiple electrical paths
    Patent number: 7183653
    Abstract: A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via having multiple electrical paths for interconnecting the first layer of conductive material and the second layer of conductive material. A method for forming a via includes drilling an opening to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Todd B Myers, Nicholas R. Watts, Eric C Palmer, Renee M Defeo, Jui Min Lim