Patents by Inventor Eric C. Samson

Eric C. Samson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190215769
    Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 11, 2019
    Applicant: Intel Corporation
    Inventors: Eric C. Samson, Murali Ramadoss, Marc Beuchat
  • Publication number: 20190107879
    Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 11, 2019
    Applicant: INTEL CORPORATION
    Inventors: Paul S. DIEFENBAUGH, Eugene GORBATOV, Andrew HENROID, Eric C. SAMSON, Barnes COOPER
  • Publication number: 20190095305
    Abstract: Methods and apparatus relating to techniques for determining idle power state are described. In an embodiment, power configuration logic determines a power state configuration for a portion of a processor. The power state configuration corresponds to a plurality of settings for operation of the portion of the processor during an idle period. Moreover, the power configuration logic determines the power state configuration based at least in part on one or more (e.g., runtime) workload measurements. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventor: Eric C. Samson
  • Patent number: 10242418
    Abstract: Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson
  • Patent number: 10242652
    Abstract: Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson
  • Patent number: 10178619
    Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Eric C. Samson, Murali Ramadoss, Marc Beuchat
  • Patent number: 10114441
    Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Paul S. Diefenbaugh, Eugene Gorbatov, Andrew Henroid, Eric C. Samson, Barnes Cooper
  • Publication number: 20180308209
    Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Publication number: 20180307533
    Abstract: A mechanism is described for facilitating multi-level scheduling of workloads in computing devices. A method of embodiments, as described herein, includes facilitating multiple levels of scheduling for processing of workloads using multiple levels of queues, where the workloads are associated with a device including a processor of a computing device.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Inventors: Kun Tian, David J. Cowperthwaite, Murali Ramadoss, Balaji Vembu, Zhi Wang, Eric C. Samson, Altug Koker, Abhishek R. Appu, Joydeep Ray
  • Publication number: 20180300845
    Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 18, 2018
    Applicant: Intel Corporation
    Inventors: Adam T. Lake, Guei-Yuan Lueh, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Abhishek R. Appu, Altug Koker, Subramaniam M. Maiyuran, Eric C. Samson, David J. Cowperthwaite, Zhi Wang, Kun Tian, David Puffer, Brian T. Lewis
  • Publication number: 20180285230
    Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Nikos Kaburlasos, Balaji Vembu, Josh B. Mastronarde, Altug Koker, Eric C. Samson, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Vasanth Ranganathan, Sanjeev S. Jahagirdar
  • Publication number: 20180285191
    Abstract: Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Sanjeev S. Jahagirdar, Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Eric C. Samson, Joydeep Ray, Travis T. Schluessler, Jacek Kwiatkowski, Abhishek R. Appu, Ankur N. Shah, Altug Koker
  • Publication number: 20180260153
    Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
    Type: Application
    Filed: October 17, 2017
    Publication date: September 13, 2018
    Inventors: Inder M. Sodhi, Alon Naveh, Doron Rajwan, Ryan D. Wells, Eric C. Samson
  • Patent number: 10043232
    Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a compute cluster including multiple compute units, a stall notification module to detect that one or more compute units in the compute cluster are stalled and send stall notification, and a rebalance module to receive the stall notification, the rebalance module to migrate a first workload from one or more stalled compute units in response to the stall notification.
    Type: Grant
    Filed: April 9, 2017
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Publication number: 20180137668
    Abstract: Methods and apparatus relating to techniques for dynamically selecting optimum graphics logic frequency and/or graphics logic power gating configuration are described. In an embodiment, multi-rate control logic determines processor active slice count and processor frequency based at least in part on a target Frames Per Second (FPS) value and a current FPS value. The multi-rate control logic includes slow rate control logic to determine slice gating and operating frequency and a fast rate control logic to determine operating frequency of the processor. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventors: Pietro Mercati, Raid Ayoub, Michael Kishinevsky, Eric C. Samson, Marc Beuchat, Francesco Paterna
  • Patent number: 9939879
    Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Jeremy J. Shrall, Eric C. Samson, Eliezer Weissmann, Ryan Wells
  • Patent number: 9852714
    Abstract: Systems and methods of adjusting a frequency of a graphics controller may include a logic to determine a metric associated with an input/output (I/O) queue. The metric may be used to determine whether an I/O limited condition exists. The I/O limited condition may be associated with a graphics controller. There may be a logic to cause a frequency of the graphics controller to be decreased when the I/O limited condition exists, and a logic to cause the frequency of the graphics controller to be increased when the I/O limited condition does not exist. The I/O limited condition may exist when a magnitude of the metric is equal to or greater than a first threshold. The I/O limited condition may not exist when the magnitude of the metric is equal to or less than a second threshold.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventor: Eric C. Samson
  • Patent number: 9805438
    Abstract: According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson, Altug Koker
  • Patent number: 9804656
    Abstract: Methods and apparatus relating to micro-architectural energy monitor event-assisted temperature sensing are described. In one embodiment, at least one of a plurality of slices of a computational logic or at least one of a plurality of sub-slices of the computational logic are powered down or powered up based on a comparison of a temperature value, that is determined based on one or more micro-architectural events, and a threshold value. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Linda L. Hurd, Eric C. Samson
  • Patent number: 9792064
    Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Inder M. Sodhi, Alon Naveh, Doron Rajwan, Ryan D. Wells, Eric C. Samson