Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.

Abstract: A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component or the master component may be a central processing unit, a graphics memory and controller hub, or a central processing unit memory controller hub. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy.

Abstract: According to some embodiments, a power budget allocation engine of a multi-component computer system may receive a power budget allocation adjustment request signal from a first component. Based on the received budget allocation adjustment request signal (and, in some embodiments, a component preference), the power budget allocation engine may determine whether to adjust a power budget allocation signal provided to the first component.

Abstract: A processor is provided with a workload that has a real-time demand. A processor clock frequency requirement is set for the processor, based on a deadline margin for the real-time demand. Other embodiments are also described and claimed.

Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.

Abstract: An embodiment may be an apparatus comprising a link coupled with a memory, and circuitry coupled with the link to calculate the amount of memory access idle time, determine if memory access idle time is sufficient to change to a self-refresh state, and change to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Another embodiment may be a method for memory to enter self-refresh comprising calculating the amount of memory access idle time, determining if memory access idle time is sufficient to change to a self-refresh state, and changing to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Various other embodiments systems, methods, machine readable mediums and apparatuses may provide similar functionality to these exemplary embodiments.

Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.

Abstract: Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

Abstract: A novel graphics system including workload detection software is disclosed. The novel graphics system increases the voltage and frequency of the graphics hardware in an integrated graphics chipset, depending on operations performed by the hardware, for either a performance advantage or a power savings advantage.

Abstract: Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

Abstract: Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in self-refresh and chipset clock circuits in power down mode while keeping the isochronous streams (such as display) updated and servicing bus master cycles in a power savings mode.

Abstract: Embodiments of the invention relate to graphics rendering in which Z-buffering tests are performed at the front of the rendering pipeline. Particularly, Z-buffering test logic at the front of the rendering pipeline is coupled to a render cache memory, which includes a Z-buffer, such that Z-buffering can be accomplished at the front of the rendering pipeline.

Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.

Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Abstract: When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

Abstract: Machine-readable media, methods, and apparatus are described to throttle interfaces and/or logic based upon a temperature estimate. Some embodiments may provide thermal effects associated with throttled and non-throttled interfaces to a filter. The filter may update a temperature estimate based upon the provided thermal effects and one or more thermal time constants. Control logic may determine whether to throttle one or more interface based upon the temperature estimate of the filter.

Abstract: Machine-readable media, methods, and apparatus are described to throttle interfaces and/or logic based upon a temperature estimate. Some embodiments may provide thermal effects associated with throttled and non-throttled interfaces to a filter. The filter may update a temperature estimate based upon the provided thermal effects and one or more thermal time constants. Control logic may determine whether to throttle one or more interface based upon the temperature estimate of the filter.

Abstract: When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

Abstract: Embodiments of the invention relate to graphics rendering in which Z-buffering tests are performed at the front of the rendering pipeline. Particularly, Z-buffering test logic at the front of the rendering pipeline is coupled to a render cache memory, which includes a Z-buffer, such that Z-buffering can be accomplished at the front of the rendering pipeline.

Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.