Patents by Inventor Eric C. Saxe

Eric C. Saxe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100332883
    Abstract: A system for dispatching a thread to a resource obtains a thread and utilization data for all resources. The system determines if there is a thread-resource affinity. The system uses thread-resource affinity to identify a resource and a timestamp for when the thread last completed executing on the resource. The system determines if the resource qualifies under a dispatch policy. The system uses utilization data to determine a timestamp for when the resource last transitioned to a not powered state. When the second timestamp precedes the first timestamp, the system dispatches the thread to the resource and generates a power management event. The system determines if the power management event satisfies a throttle policy. The system discards the power management event when throttle policy is unsatisfied and determines whether to adjust the current power state of the resource based on the power management event when throttle policy is satisfied.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Eric C. Saxe, Darrin P. Johnson, William D. Holler
  • Publication number: 20090327602
    Abstract: A method for wear level-based allocation in a storage pool. The method includes receiving a first request to write a first data item in a storage pool, where the storage pool includes a number of physical locations associated with the storage devices, and where each of the storage devices includes metadata regarding a level of wear of the storage device. The method further includes determining a first target physical location selected from the plurality of physical locations by using a wear-level selection policy and a wear cost for each of the storage devices, where the wear cost is determined based on a type of the storage device. The method further includes allocating a first data block to the first target physical location writing the first data block to the first target physical locations, wherein the first data block comprises a first portion of the first data item.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: William H. Moore, Darrin P. Johnson, Eric C. Saxe
  • Publication number: 20090320000
    Abstract: A method for power managing hardware. The method includes determining hardware to power manage, sending a tracing request from a power management control to a tracing framework to obtain usage data of the hardware, and identifying a first probe to obtain first tracing data corresponding to the usage data in a first hardware control software component, where the first hardware control software is configured to interact with the hardware. The method further includes enabling the first probe, obtaining the first tracing data from the first probe, where the first tracing data is obtained when the first probe is encountered during execution of the first hardware control software, and modifying operation of the hardware using the first tracing data.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Eric C. Saxe, Darrin P. Johnson, Jonathan J. Chew
  • Publication number: 20090300299
    Abstract: Methods and apparatus provide for a Dynamic Interleaver to modify the interleaving distribution spanning physical memory modules. Specifically, dynamic interleaving provides the ability to increase the number of interleaved physical memory modules when a current interleaved group of memory locations is experiencing heavy use. By increasing the number of interleaved memory locations, a system can make optimal use of memory by allowing more parallel accesses to physical memory during the period of heavy utilization. However, if the current interleaved group of memory locations experience low use, the Dynamic Interleaver can choose to interleave across fewer physical memory modules and apply power management techniques to those memory locations that are no longer being accessed. Prior to “re-interleaving” interleaved memory locations, the Dynamic Interleaver migrates data out of the current interleaved memory locations.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 3, 2009
    Inventors: Eric C. Saxe, Sherry Q. Moore, Darrin P. Johnson
  • Patent number: 7614056
    Abstract: An abstraction layer is comprised in the operating system that represents the particulars of the PPMs. The abstractions in the abstraction layer are differentiated from one another by parameters representing the characteristics of the PPMs. The dispatcher uses the abstraction to balance processing loads when assigning execution threads to the PPMs. The assigning of the execution threads and the balancing of the processing loads is performed while taking account of the characteristics of the PPMs, such as shared resources and clock speed.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: November 3, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Eric C. Saxe, Andrei Dorofeev, Jonathan Chew, Bart Smaalders, Andrew G. Tucker
  • Publication number: 20090089531
    Abstract: A method for memory management that includes receiving a request for memory space, identifying a first memory module from a plurality of memory modules based on a first memory power management policy, wherein the first memory power management policy specifies how to allocate memory space in the plurality of memory modules to satisfy a power consumption criteria, and allocating the memory space on the first memory module.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: Sun Microsystems, Inc.
    Inventors: Darrin P. Johnson, Eric C. Saxe, Sherry Q. Moore
  • Publication number: 20090089780
    Abstract: In general, embodiments of the invention relates to a method for conveying hardware resources from a host (OS) executing on a computer system. The method includes obtaining host hardware information by the host OS, wherein the host hardware information specifies a plurality of physical hardware components of the computer system, sending the host hardware information to a guest OS executing within the host OS, generating, by the guest OS, a resource request using the host hardware information, sending, by the guest OS, the resource request to the host OS, and in response to receiving the resource request, allocating, by the host OS, guest hardware resources, where the guest hardware resources include at least one of the physical hardware components in the resource request.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Darrin P. Johnson, Eric C. Saxe, Jonathan J. Chew
  • Publication number: 20090089782
    Abstract: In general the invention relates to a system. The system includes processors each having a processing state. The system further includes a dispatcher operatively connected to the plurality of processors and configured to: receive a first thread to dispatch, select one of the processors to dispatch the thread to based on the processing state the processors and a power management policy, and dispatch the thread to the selected one of the plurality of processors.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Darrin P. Johnson, Eric C. Saxe, Bart Smaalders
  • Publication number: 20090089792
    Abstract: In general, the invention relates to a system that includes a multi-core processor and a dispatcher operatively connected to the multi-core processor. The dispatcher is configured to receive a first plurality of threads during a first period of time, dispatch the first plurality of threads only to a first core of the plurality of cores, receive a second plurality of threads during a second period of time, dispatch the second plurality of threads only to a second core of the plurality of cores, migrate to the second core any of the first plurality of threads that are still executing on the first after the first period of time has elapsed. The duration of the first period of time and the duration of the second period of time are determined using a thread migration schedule, and thread migration schedule is determined using at least one thermal characteristic of the multi-core processor.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Darrin P. Johnson, Eric C. Saxe, Bart Smaalders
  • Publication number: 20080117824
    Abstract: One embodiment of the present invention provides a system that facilitates improved resource allocation in a network. During operation, the system determines one or more metrics value for a node based on a characteristic of the node and assigns nodes within the network to access groups based on each node's characteristic-metric value and a grouping policy. The system further constructs a logical hierarchy of access groups based on the characteristic-metric values of the nodes within each access group. Additionally, the system allows a node to forward traffic to a next-hop node identified within an access group on a logical hierarchy level, thereby facilitating better resource allocation in the network.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 22, 2008
    Inventors: Samita Chakrabarti, Darrin P. Johnson, Eric C. Saxe