Patents by Inventor Eric C. T. Harley
Eric C. T. Harley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9577099Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.Type: GrantFiled: March 9, 2015Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Veeraraghavan S. Basker, Eric C. T. Harley, Yue Ke, Alexander Reznicek, Henry K. Utomo
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Patent number: 9536985Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.Type: GrantFiled: September 29, 2014Date of Patent: January 3, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Brian J. Greene, Eric C. T. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Renee T. Mo, Yinxiao Yang
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Patent number: 9466616Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.Type: GrantFiled: February 26, 2016Date of Patent: October 11, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Eric C. T. Harley, Judson R. Holt, Yue Ke, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek
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Publication number: 20160268413Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.Type: ApplicationFiled: March 9, 2015Publication date: September 15, 2016Inventors: Veeraraghavan S. Basker, Eric C. T. Harley, Yue Ke, Alexander Reznicek, Henry K. Utomo
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Publication number: 20160181285Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.Type: ApplicationFiled: February 26, 2016Publication date: June 23, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Eric C.T. Harley, Judson R. Holt, Yue Ke, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek
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Publication number: 20160163707Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.Type: ApplicationFiled: February 5, 2016Publication date: June 9, 2016Inventors: Kangguo Cheng, Eric C.T. Harley, Judson R. Holt, Gauri V. Karve, Yue Ke, Derrick Liu, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek, Melissa Alyson Smith
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Patent number: 9318608Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.Type: GrantFiled: September 29, 2014Date of Patent: April 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Eric C. T. Harley, Judson R. Holt, Yue Ke, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek
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Publication number: 20160093740Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Eric C. T. Harley, Judson R. Holt, Yue Ke, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek
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Publication number: 20160093720Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Michael P. Chudzik, Brian J. Greene, Eric C. T. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Renee T. Mo, Yinxiao Yang
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Patent number: 9287264Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.Type: GrantFiled: December 5, 2014Date of Patent: March 15, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Kangguo Cheng, Eric C. T. Harley, Judson R. Holt, Gauri V. Karve, Yue Ke, Derrick Liu, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek, Melissa A. Smith
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Patent number: 8361859Abstract: An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.Type: GrantFiled: November 9, 2010Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Stephen W. Bedell, Abhishek Dube, Eric C. T. Harley, Judson R. Holt, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis, Matthew W. Stoker, Keith H. Tabakman
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Publication number: 20120228716Abstract: A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.Type: ApplicationFiled: May 23, 2012Publication date: September 13, 2012Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., ADVANCED MICRO DEVICES, INC.Inventors: Eric C. T. Harley, Judson R. Holt, Dominic J. Schepis, Michael D. Steigerwalt, Linda Black, Rick Carter
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Patent number: 8232186Abstract: Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.Type: GrantFiled: May 29, 2008Date of Patent: July 31, 2012Assignees: International Business Machines Corporation, GlobalfoundriesInventors: Eric C. T. Harley, Judson R. Holt, Dominic J. Schepis, Michael D. Steigerwalt, Linda Black, Rick Carter
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Publication number: 20120112208Abstract: An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.Type: ApplicationFiled: November 9, 2010Publication date: May 10, 2012Applicant: International Business Machines CorporationInventors: THOMAS N. ADAM, Stephen W. Bedell, Abhishek Dube, Eric C.T. Harley, Judson R. Holt, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis, Matthew W. Stoker, Keith H. Tabakman
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Patent number: 8084788Abstract: A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.Type: GrantFiled: October 10, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Judson Robert Holt, Abhishek Dube, Eric C. T. Harley, Shwu-Jen Jeng, Jeremy J Kempisty, Hasan Munir Nayfeh, Keith Howard Tabakman
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Patent number: 8080451Abstract: Solutions for fabricating a semiconductor structure. One embodiment includes a method for fabricating a semiconductor structure, the method including: forming a first dielectric structure on a substrate, the first dielectric structure including silicon nitride (Si3N4); forming a second dielectric structure in proximity to the first dielectric structure; and growing a non-epitaxial thin film from a surface of the first dielectric structure; wherein the growing includes using a combination of precursor, carrier and etchant with a ratio among the precursor, carrier, and etchant being adjusted for selective growth of the thin film on the surface, and wherein the thin film includes one selected from a group consisting of: a monocrystalline material, an amorphous material, a polycrystalline material and a combination thereof.Type: GrantFiled: January 8, 2010Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Ashima B. Chakravarti, Eric C. T. Harley, Judson R. Holt
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Publication number: 20100112762Abstract: Methods of fabricating a semiconductor structure with a non- epitaxial thin film disposed on a surface of a substrate of the semiconductor structure are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process.Type: ApplicationFiled: January 8, 2010Publication date: May 6, 2010Inventors: Thomas N. Adam, Ashima B. Chakravarti, Eric C.T. Harley, Judson R. Holt
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Publication number: 20100090288Abstract: A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.Type: ApplicationFiled: October 10, 2008Publication date: April 15, 2010Applicant: International Business Machines CorporationInventors: Judson R. Holt, Abhishek Dube, Eric C.T. Harley, Shwu-Jen Jeng, Jeremy J. Kempisty, Hasan Munir Nayfeh, Keith Howard Tabakman
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Patent number: 7687804Abstract: Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process.Type: GrantFiled: January 8, 2008Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Ashima B. Chakravarti, Eric C. T. Harley, Judson R. Holt
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Publication number: 20090294801Abstract: Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.Type: ApplicationFiled: May 29, 2008Publication date: December 3, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC.Inventors: Eric C. T. Harley, Judson R. Holt, Dominic J. Schepis, Michael D. Steigerwalt, Linda Black, Rick Carter