Abstract: A communications network includes multiple distributed nodes that are coupled by a circuit-switched network. To improve efficiency, a plurality of the nodes are associated with a single source synchronization block that injects timing messages over circuits in the circuit-switched network to the plurality of nodes. Each of the plurality of nodes is associated with a timing extraction and recovery block that extracts information from the timing messages injected by the source synchronization block to synchronize a local clock in each node to the frequency and phase of a clock received by the source synchronization block.

Abstract: A communications network includes multiple distributed nodes that are coupled by a circuit-switched network. To improve efficiency, a plurality of the nodes are associated with a single source synchronization block that injects timing messages over circuits in the circuit-switched network to the plurality of nodes. Each of the plurality of nodes is associated with a timing extraction and recovery block that extracts information from the timing messages injected by the source synchronization block to synchronize a local clock in each node to the frequency and phase of a clock received by the source synchronization block.

Abstract: A communications network includes multiple distributed nodes that are coupled by a circuit-switched network. To improve efficiency, a plurality of the nodes are associated with a single source synchronization block that injects timing messages over circuits in the circuit-switched network to the plurality of nodes. Each of the plurality of nodes is associated with a timing extraction and recovery block that extracts information from the timing messages injected by the source synchronization block to synchronize a local clock in each node to the frequency and phase of a clock received by the source synchronization block.

Abstract: A feed forward power amplifier has a main amplifier and an error compensation path that compares the input and output of the main amplifier and subsequently adjusts the output signal from the main amplifier. Currently, such a design requires the implementation of a delay apparatus to delay the output of the main amplifier in order to compensate for the delay within the error compensation path. This delay apparatus implemented within a high-power area costs the power amplifier in terms of money, size, and/or efficiency. With the implementation of a phase compensation filter within the error compensation path, the delay apparatus can be removed. The phase compensation filter has a frequency versus phase characteristic with a positive slope for a limited bandwidth and a constant frequency versus gain characteristic. This allows, for the limited bandwidth, the characteristic of the error compensation path to be similar to that of the undelayed output of the main amplifier.