Abstract: A pipelined digital computer processor system (10, FIG. 1) is provided comprising an instruction prefetch unit (IPU,2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions. The IPU (2) has associated with it a high speed instruction cache (6), and the ALPU (4) has associated with it a high speed operand cache (8). Each cache comprises a data store (84, 94, FIG. 3) for storing frequently accessed data, and a tag store (82, 92, FIG. 3) for indicating which main memory locations are contained in the respective cache.The IPU and ALPU processing units (2, 4) may access their associated caches independently under most conditions. When the ALPU performs a write operation to main memory, it also updates the corresponding data in the operand cache and, if contained therein, in the instruction cache permitting the use of self-modifying code. The IPU does not write to either cache.

Abstract: In an electronic system, such as a digital data processing system, comprising a number of circuit boards, each circuit board being of a particular functional type and also uniquely identifiable by a manufacturing revision number, there is provided a status detection circuit for polling various programmable status information from the board, including a unique board identity number and the manufacturing revision number. The status detection circuit includes a microcomputer (60, FIG. 2) on each board 50. The data inputs of the microcomputer are responsive to a unique combination of switches (e.g., 42) representative of the manufacturing revision number. Other microcomputer inputs are responsive to a unique combination of edge connectors (e.g., 47) for uniquely identifying the particular board in the system. Another microcomputer input is responsive to an on-board status indicator, such as an LED.