Patents by Inventor Eric Chesters
Eric Chesters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8270231Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.Type: GrantFiled: October 26, 2010Date of Patent: September 18, 2012Assignee: Infineon Technologies AGInventors: Klaus J. Oberlaender, Ralph Haines, Eric Chesters, Dirk Behrens
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Publication number: 20110032029Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.Type: ApplicationFiled: October 26, 2010Publication date: February 10, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Klaus J. OBERLAENDER, Ralph Haines, Eric Chesters, Dirk Behrens
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Patent number: 7821849Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.Type: GrantFiled: February 8, 2008Date of Patent: October 26, 2010Assignee: Infineon Technologies AGInventors: Klaus J. Oberlaender, Ralph Haines, Eric Chesters, Dirk Behrens
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Publication number: 20080195835Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.Type: ApplicationFiled: February 8, 2008Publication date: August 14, 2008Applicant: Infineon Technologies AGInventors: KLAUS J. OBERLAENDER, RALPH HAINES, ERIC CHESTERS, DRIK BEHRENS
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Patent number: 7339837Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.Type: GrantFiled: May 18, 2004Date of Patent: March 4, 2008Assignee: Infineon Technologies AGInventors: Klaus J. Oberlaender, Ralph Haines, Eric Chesters, Dirk Behrens
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Publication number: 20050258517Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.Type: ApplicationFiled: May 18, 2004Publication date: November 24, 2005Applicant: Infineon Technologies NA Corp.Inventors: Klaus Oberlaender, Ralph Haines, Eric Chesters, Dirk Behrens
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Patent number: 6516428Abstract: An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an integrated circuit. The data band selector is directed by the emulator based upon instructions received from a host computer.Type: GrantFiled: January 22, 1999Date of Patent: February 4, 2003Assignee: Infineon Technologies AGInventors: Andreas Wenzel, Eric Chesters, Rod G. Fleck, Gary Sheedy
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Publication number: 20020147939Abstract: An improved on chip debug system is disclosed. The on chip debug system includes a data band selector arranged to selectively transmit particular data bands generated by a processor included in an integrated circuit as needed to an emulator. The data band selector is directed by the emulator based upon instructions received from a host computer.Type: ApplicationFiled: January 22, 1999Publication date: October 10, 2002Inventors: ANDREAS WENZEL, ERIC CHESTERS, ROD G. FLECK, GARY SHEEDY
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Patent number: 6393551Abstract: A method and an apparatus for reducing the number of instruction transactions in a microprocessor are disclosed. As a method, the number of issued instructions carried by an issued instruction bus in a computer system are reduced by determining if an instruction fetched by a fetch unit matches a cached instruction tag. When the fetched instruction matches the cached instruction tag, an opcode and an associated instruction corresponding to the cached instruction tag are directly injected to an appropriate function unit. The apparatus includes a plurality of tag PC cache memory devices used to store tag PC entries associated with target instructions injected directly to corresponding function units included microprocessors and the like. The injection reduces the number of instructions fetched from the program memory as well as the number of issued instructions carried by an issued instruction bus.Type: GrantFiled: May 26, 1999Date of Patent: May 21, 2002Assignee: Infineon Technologies North America Corp.Inventors: Balraj Singh, Eric Chesters, Venkat Mattela, Rod G. Fleck
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Patent number: 6175913Abstract: A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.Type: GrantFiled: September 12, 1997Date of Patent: January 16, 2001Assignee: Siemens AGInventors: Eric Chesters, Roger D. Arnold, Rod G. Fleck
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Patent number: 6128641Abstract: The present invention relates to a method of context switching from a first task to a second task in a data processing unit having a register file with a plurality of general purpose registers and a context switch register, a memory comprising a previous context save area and an unused context save area. The memory is coupled with the register file and an instruction control unit with a program counter register and a program status word register coupled with the memory and the register file. The method comprises the steps of acquiring a new save area from said unused save area, storing the context of the first task in said new area, linking the new area with said previous context save area.Type: GrantFiled: September 12, 1997Date of Patent: October 3, 2000Assignee: Siemens AktiengesellschaftInventors: Rod G. Fleck, Roger D. Arnold, Bruce Holmer, Vojin G. Oklobdzija, Eric Chesters
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Patent number: 6085315Abstract: The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.Type: GrantFiled: September 12, 1997Date of Patent: July 4, 2000Assignee: Siemens AktiengesellschaftInventors: Rod G. Fleck, Venkat Mattela, Eric Chesters, Muhammad Afsar
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Patent number: D904507Type: GrantFiled: January 14, 2019Date of Patent: December 8, 2020Assignee: ADP, LLCInventors: Eric Chester-Jenkins, Ali Madad
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Patent number: D904508Type: GrantFiled: January 14, 2019Date of Patent: December 8, 2020Assignee: ADP, LLCInventors: Eric Chester-Jenkins, Ali Madad
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Patent number: D904509Type: GrantFiled: January 14, 2019Date of Patent: December 8, 2020Assignee: ADP, LLCInventors: Eric Chester-Jenkins, Ali Madad
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Patent number: D904510Type: GrantFiled: January 14, 2019Date of Patent: December 8, 2020Assignee: ADP, LLCInventors: Eric Chester-Jenkins, Ali Madad
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Patent number: D913368Type: GrantFiled: January 14, 2019Date of Patent: March 16, 2021Assignee: ADP, LLCInventors: Eric Chester-Jenkins, Ali Madad