Abstract: In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Abstract: In a general aspect, a computer system includes a low-latency communication link between a classical computer and a quantum computing resource. In some cases, a quantum machine image operates on a classical computer system. The quantum machine image includes a virtualized execution environment for quantum programs. The quantum machine image is engaged with a quantum processing unit of a quantum computing system. A quantum program is communicated over a low-latency communication pathway from the classical computer system to the quantum computer system. The quantum program is executed at the quantum computer system.

Abstract: Techniques for training local decoders for use in a local and global decoding scheme for quantum error correction of circuit-level noise within quantum surface codes such that the decoding schemes have fast decoding throughout and low latency times for quantum algorithms are disclosed. The local decoders may have a neural network architecture and may be trained using training data sets comprising simulated rounds of syndrome measurements for respective simulated quantum surface codes in addition to information such as syndrome differences, qubit placements, and temporal boundaries within the simulated rounds of syndrome measurements in order to train the local decoders for arbitrarily sized quantum surface codes and arbitrary numbers of rounds of syndrome measurements. Following a local decoding stage in which a large number of data errors have been corrected by a local decoder, error correction for remaining errors may continue with a more efficient global decoding stage.

Abstract: In a general aspect, a computer system includes a low-latency communication link between a classical computer and a quantum computing resource. In some cases, a quantum machine image operates on a classical computer system. The quantum machine image includes a virtualized execution environment for quantum programs. The quantum machine image is engaged with a quantum processing unit of a quantum computing system. A quantum program is communicated over a low-latency communication pathway from the classical computer system to the quantum computer system. The quantum program is executed at the quantum computer system.

Abstract: Techniques for implementing a local neural network and global decoding scheme for quantum error correction of circuit-level noise within quantum surface codes such that the decoding schemes have fast decoding throughout and low latency times for quantum algorithms are disclosed. A local neural network decoder may be pre-trained via a supervised learning technique such that the local neural network decoder may be applied for error correction in the presence of circuit-level noise in arbitrarily sized surface codes in a local decoding stage. Prior to a global decoding stage, an intermediate stage may be used to remove vertical pairs of highlighted vertices within the matching graph, which may reduce a syndrome density within the matching graph to allow for faster decoding at the global decoding stage. Such an intermediate stage may include application of a syndrome collapse or vertical cleanup technique.

Abstract: In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Abstract: In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Abstract: A compiler for a gate-based superconducting quantum computer compiles hybrid classical/quantum algorithms for quantum processing cells with different configurations. The compiler inputs the algorithm and outputs code in a target language executable by a quantum processing cell of a quantum processing system that can execute the algorithm. The compiler includes various functionality, such as: parsing, analyzing control flows, addressing, compressing, and translating. The compiler optimizes algorithms in various manners using the functionality. Some optimizations include addressing efficiently, compressing based on simulations, and translating for efficient execution of parametric functions. The compiler may function in the environment of a cloud quantum computing system. The cloud quantum computing system may receive algorithms from remote access nodes for execution on local classical and quantum computing systems.

Abstract: In a general aspect, methods and systems are described for dynamically partitioning and virtualizing a monolithic quantum-classical hybrid computing resource into multiple different and independently-saleable, as a resource to a user, parcels. These parcels may comprise configurations of qubits and qubit-qubit links on one or more quantum processor units for use by users for running computer programs.

Abstract: In a general aspect, a computer system includes a low-latency communication link between a classical computer and a quantum computing resource. In some cases, a quantum machine image operates on a classical computer system. The quantum machine image includes a virtualized execution environment for quantum programs. The quantum machine image is engaged with a quantum processing unit of a quantum computing system. A quantum program is communicated over a low-latency communication pathway from the classical computer system to the quantum computer system. The quantum program is executed at the quantum computer system.

Abstract: A compiler translates programs for execution on a quantum processing system. To facilitate portability of quantum programs across differently configured quantum processors, the compiler accepts a specification of the quantum processor as input along with a quantum program for compilation. A specification may include information about the type of each qubit device in the quantum processor, the number of qubits, the qubit topology, coherence times of individual qubits, and operations that the quantum processor supports. The compilation process may include manipulating operations of the input program to generate equivalent operations that can be performed by the quantum gates and qubit devices on the quantum processor for which the program is being compiled.