Abstract: A smart NIC (Network Interface Card) is provided with features to enable the smart NIC to operate as an in-line NIC between a host's NIC and a network. The smart NIC provides pass-through transmission of network flows for the host. Packets sent to and from the host pass through the smart NIC. As a pass-through point, the smart NIC is able to accelerate the performance of the pass-through network flows by analyzing packets, inserting packets, dropping packets, inserting or recognizing congestion information, and so forth. In addition, the smart NIC provides a lightweight transport protocol (LTP) module that enables it to establish connections with other smart NICs. The LTP connections allow the smart NICs to exchange data without passing network traffic through their respective hosts.

Abstract: Various embodiments of methods and systems for saving coins and applying the coin value toward the purchase of selected products are disclosed herein. In some embodiments, the methods and systems described herein can be utilized by parents, grandparents, etc. to encourage and facilitate saving by children. For example, in some embodiments a mobile application is provided that enables a child to select a product to purchase as a “reward” for achieving a savings goal. The mobile application can also enable the child (and/or the child's parent) to set the savings goal, and track the child's progress in reaching the goal as saved coins are periodically exchanged at one or more coin counting kiosks. Other embodiments of the disclosed technology enable the parent and/or child to receive a notification when the child reaches the savings goal, and apply the saved funds toward the purchase of the selected reward.

Abstract: Systems and methods are described herein for incentivizing consumers to recycle their accumulated change at consumer-operated coin counting kiosks. In various embodiments, the methods can include providing users with a plurality of deals on, e.g., leisure time activities and other rewarding goods and services that they can purchase at the coin counting kiosks in return for loose coins. The systems can include a software application, e.g., a mobile application that can be used to obtain user deal preferences and periodically provide users with deal offers that match their preferences and/or the amount of coin value they may have available to put toward a purchase. Other embodiments of the disclosed technology enable multiple users to purchase deals (e.g., group activities) as a group by making individual contributions toward the purchase price via a network of coin counting kiosks.

Abstract: A smart NIC (Network Interface Card) is provided with features to enable the smart NIC to operate as an in-line NIC between a host's NIC and a network. The smart NIC provides pass-through transmission of network flows for the host. Packets sent to and from the host pass through the smart NIC. As a pass-through point, the smart NIC is able to accelerate the performance of the pass-through network flows by analyzing packets, inserting packets, dropping packets, inserting or recognizing congestion information, and so forth. In addition, the smart NIC provides a lightweight transport protocol (LTP) module that enables it to establish connections with other smart NICs. The LTP connections allow the smart NICs to exchange data without passing network traffic through their respective hosts.

Abstract: A method is provided for processing on an acceleration component a machine learning classification model. The machine learning classification model includes a plurality of decision trees, the decision trees including a first amount of decision tree data. The acceleration component includes an acceleration component die and a memory stack disposed in an integrated circuit package. The memory die includes an acceleration component memory having a second amount of memory less than the first amount of decision tree data. The memory stack includes a memory bandwidth greater than about 50 GB/sec and a power efficiency of greater than about 20 MB/sec/mW.

Abstract: A smart NIC (Network Interface Card) is provided with features to enable the smart NIC to operate as an in-line NIC between a host's NIC and a network. The smart NIC provides pass-through transmission of network flows for the host. Packets sent to and from the host pass through the smart NIC. As a pass-through point, the smart NIC is able to accelerate the performance of the pass-through network flows by analyzing packets, inserting packets, dropping packets, inserting or recognizing congestion information, and so forth. In addition, the smart NIC provides a lightweight transport protocol (LTP) module that enables it to establish connections with other smart NICs. The LTP connections allow the smart NICs to exchange data without passing network traffic through their respective hosts.

Abstract: A server unit component is provided that includes a host component including a CPU, and an acceleration component coupled to the host component. The acceleration component includes an acceleration component die and a memory stack. The acceleration component die and the memory stack are disposed in an integrated circuit package. The memory stack has a memory bandwidth greater than about 50 GB/sec and a power efficiency of greater than about 20 MB/sec/mW.

Abstract: A method is provided for implementing a deep neural network on a server component that includes a host component including a CPU and a hardware acceleration component coupled to the host component. The deep neural network includes a plurality of layers. The method includes partitioning the deep neural network into a first segment and a second segment, the first segment including a first subset of the plurality of layers, the second segment including a second subset of the plurality of layers, configuring the host component to implement the first segment, and configuring the hardware acceleration component to implement the second segment.

Abstract: A method is provided for processing on an acceleration component a deep neural network. The method includes configuring the acceleration component to perform forward propagation and backpropagation stages of the deep neural network. The acceleration component includes an acceleration component die and a memory stack disposed in an integrated circuit package. The memory stack has a memory bandwidth greater than about 50 GB/sec and a power efficiency of greater than about 20 MB/sec/mW.

Abstract: A hardware acceleration component is provided for implementing a convolutional neural network. The hardware acceleration component includes an array of N rows and M columns of functional units, an array of N input data buffers configured to store input data, and an array of M weights data buffers configured to store weights data. Each of the N input data buffers is coupled to a corresponding one of the N rows of functional units. Each of the M weights data buffers is coupled to a corresponding one of the M columns of functional units. Each functional unit in a row is configured to receive a same set of input data. Each functional unit in a column is configured to receive a same set of weights data from the weights data buffer coupled to the row. Each of the functional units is configured to perform a convolution of the received input data and the received weights data, and the M columns of functional units are configured to provide M planes of output data.

Abstract: A universal single-bitstream FPGA library or ASIC implementation accelerates matrix-vector multiplication processing multiple matrix encodings including dense and multiple sparse formats. A hardware-optimized sparse matrix representation referred to herein as the Compressed Variable-Length Bit Vector (CVBV) format is used to take advantage of the capabilities of FPGAs and reduce storage and bandwidth requirements across the matrices compared to that typically achieved when using the Compressed Sparse Row (CSR) format in typical CPU- and GPU-based approaches. Also disclosed is a class of sparse matrix formats that are better suited for FPGA implementations than existing formats reducing storage and bandwidth requirements. A partitioned CVBV format is described to enable parallel decoding.

Abstract: A universal single-bitstream FPGA library or ASIC implementation accelerates matrix-vector multiplication processing multiple matrix encodings including dense and multiple sparse formats. A hardware-optimized sparse matrix representation referred to herein as the Compressed Variable-Length Bit Vector (CVBV) format is used to take advantage of the capabilities of FPGAs and reduce storage and bandwidth requirements across the matrices compared to that typically achieved when using the Compressed Sparse Row (CSR) format in typical CPU- and GPU-based approaches. Also disclosed is a class of sparse matrix formats that are better suited for FPGA implementations than existing formats reducing storage and bandwidth requirements. A partitioned CVBV format is described to enable parallel decoding.

Abstract: Apparatus, methods, and programs for protecting data on a wireless device may include a wireless device having a computer platform with a processing engine operable, based upon configurable parameters, to log data access attempt on the wireless device and transmit the log to a remote device. Furthermore, the wireless device may be configured to execute locally and remotely generated control commands on the wireless device, the commands operable to modify an operation of the wireless device. The embodiment may also include an apparatus operable to receive the transmitted log, analyze the received log and transmit a control command to the wireless device. The apparatus may further generate a data access report and make the report available to an authorized user.

Abstract: Apparatus and methods for estimating a geographical position corresponding to an event associated with operation of a wireless device communicating in a wireless communications network. The time and distance between the occurrence of the event and the related time and speed of the wireless device of at least one of a first and second geographical position, respectively measured before and after the event, are analyzed. These analyses includes comparing those metrics to predetermined time and distance thresholds to associate and/or estimate a geographic position of the wireless device with the event.

Abstract: A radiation fin set comprising a plurality of metallic radiation fins arranged in parallel for direct welding/bonding to a beat dissipation base panel or mounting on a heat dissipation tube at the heat dissipation base panel, the radiation fins each having a plurality of elongated slots and a plurality of flanges respectively extended along one side of each of the elongated slots and sloping in one direction at an angle of slope for guiding the flow of air of high momentum into mixing with the flow of air of low momentum to repress the formation of boundary layer and to improve heat dissipation efficiency of the radiation fins.

Abstract: An electronic stabilizer having a variable frequency soft start circuit, said circuit having a secondary coil coupled to a drive transformer of the electronic stabilizer. In the initial period when power is connected, the secondary coil may supply an induced voltage to a capacitor to generate a forward voltage to connect primary transistor to allow an inductance element to parallel the secondary coil to reduce the total inductance. The operating frequency of an LC oscillating circuit of the stabilizer hence increases. Relatively, the energy obtainable by the fluorescent lamp is reduced. The soft start circuit is further provided with a discharge loop of a secondary transistor for discharging of the capacitor to ensure that soft starts may be achieved under any conditions.