Patents by Inventor Eric Conway

Eric Conway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250013753
    Abstract: The present disclosure provides systems and methods that support identification of vulnerabilities within a dataset, such as an unknown binary, using customizable pipelines and workflows. The pipelines may be configured to apply various analysis techniques, including reverse engineering, machine learning/artificial intelligence, and other techniques to elicit various types of data and information from the unknown binary. The pipeline may include stages configured to analyze outputs of prior stages of the pipeline detect whether vulnerabilities or malicious code are present. Different stages of the pipeline may also be configured to initiate additional workflows for further analysis of the binary or intermediate representations of the binary output by prior stages of the pipeline. Additionally, the disclosed systems and methods provide functionality that enables generation of a reverse software bill of materials (SBOM) from an unknown binary or confirmation of contents of an existing SBOM.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Inventor: Eric Conway
  • Publication number: 20050097485
    Abstract: A methodology for improving the timing of specific critical paths in a Field Programmable Gate Array (FPGA) implementation of a logic circuit without significantly affecting the timing of other logic paths. The method utilizes logic replication and specific guidelines for placement of the logic gates involved in a critical path to optimize the timing of that critical path. The logic gates involved in a critical path are either replicated and placed, or simply moved, in order to implement the desired logic with nearly the shortest total distance for routing of signals involved in the critical path. The optimization is carried out with relatively little impact on the timing of other paths and is applicable to FPGAs in which the signal delay between any source and gate is relatively independent of the fanout of the source signal to any other loads.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 5, 2005
    Inventors: Russell Guenthner, David Selway, Clinton Eckard, Charles Ryan, Eric Conway