Abstract: The present invention provides a method and a computer system that compares a portion of a signal and information transferred from a cache memory, while the information is in transit from the cache memory. The information may be routed differently depending on the outcome of the compare. Specifically, the information may be delivered to a memory bus when it matches the portion of the signal and when the signal is a read command. Alternatively, the information may not be delivered to a memory bus when it matches the portion of the signal and when the signal is a write command. If the information does not match the portion of the signal, it may be transferred to a main memory via a memory bus. The information may be compared to the portion of the signal for a first time interval, and the portion of the signal may be compared to the information for a second time interval.

Abstract: A single ASIC memory controller has full interconnectivity between various modes on the ASIC: input controller, memory controller, and output controller. The single ASIC includes an input controller section, a memory controller section, and an output controller section. The ASIC architecture is designed to allow any of the sections to be bypassed. Using the bypass mechanism, the ASIC can be combined with other like ASICs to increase system performance and capabilities without the need for ASIC redesign. The ASIC design can be used in memory subsystems that are scalable depending on user requirements.