Abstract: A semiconductor device includes circuitry configured to derive a physical unclonable function. The circuitry includes a plurality of bitcells, each bitcell being readable as one of a ‘0’ value and a ‘1’ value, and sense amplifier circuitry configurable to read values from the plurality of bitcells. The sense amplifier circuitry includes margin circuitry configurable (i) to selectably bias reading of the plurality of bitcells toward one of ‘0’ values and ‘1’ values, (ii) to identify addresses of bitcells having a stable ‘1’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘0’ values, and (iii) to identify addresses of bitcells having a stable ‘0’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘1’ values. Each bitcell in the plurality of bitcells may include a differential transistor pair.

Abstract: A voltage power switch includes circuitry configured to output a known voltage. The voltage power switch includes a lock circuit configured to output a known state and a voltage level shifter configured to receive an input, the input being based on the known state output by the lock circuit. The voltage power switch, using an output circuit, is configured to output a known voltage level based on an output of the voltage level shifter, wherein the known voltage is one of a high voltage VHI for a fuse programing period or a first non-zero intermediate voltage VMID1 for a non-fuse programming period.

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

Abstract: The present disclosure relates to in-memory computing using a static random access memory (SRAM). In particular, the present disclosure relates to a structure including a memory configured to store a first word and a second word, the memory further includes a configurable data path circuit, and the configured data path circuit is configured to perform an arithmetic logical operation based on the first word and the second word in parallel.

Abstract: A voltage power switch includes circuitry configured to output a known voltage. The voltage power switch includes a lock circuit configured to output a known state and a voltage level shifter configured to receive an input, the input being based on the known state output by the lock circuit. The voltage power switch, using an output circuit, is configured to output a known voltage level based on an output of the voltage level shifter, wherein the known voltage is one of a high voltage VHI for a fuse programing period or a first non-zero intermediate voltage VMID1 for a non-fuse programming period.

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit incudes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

Abstract: The present disclosure relates to in-memory computing using a static random access memory (SRAM). In particular, the present disclosure relates to a structure including a memory configured to store a first word and a second word, the memory further includes a configurable data path circuit, and the configured data path circuit is configured to perform an arithmetic logical operation based on the first word and the second word in parallel.

Abstract: The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N?1 of the consecutive read operations, and N is an integer number of the consecutive read operations.

Abstract: Embodiments of the disclosure provide a system for detecting and monitoring a crack in an integrated circuit (IC), including: at least one electrically conductive perimeter line (PLINE) extending about, and electrically isolated from, a protective structure formed in an inactive region of the IC, wherein an active region of the IC is enclosed within the protective structure; a circuit for sensing a change in an electrical characteristic of the at least one PLINE, the change in the electrical characteristic indicating a presence of a crack in the inactive region of the IC; and a connecting structure for electrically coupling each PLINE to the sensing circuit.

Abstract: The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Abstract: A charge pump circuit includes a charge pump configured to increase a voltage of an input signal to generate a voltage-boosted input signal, output the voltage-boosted input signal in response to a determination that the voltage-boosted input signal is greater than or equal to a threshold, and connect the charge pump to a supply voltage to pre-charge the charge pump in response to a determination that the voltage-boosted input signal is less than the threshold. The charge pump circuit includes bandgap reference generator configured to receive the voltage-boosted input signal and output, based on the voltage-boosted input signal, a voltage reference signal to a device that operates in accordance with the supply voltage.

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Abstract: The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.

Abstract: The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.

Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

Abstract: A charge pump circuit includes a charge pump configured to increase a voltage of an input signal to generate a voltage-boosted input signal, output the voltage-boosted input signal in response to a determination that the voltage-boosted input signal is greater than or equal to a threshold, and connect the charge pump to a supply voltage to pre-charge the charge pump in response to a determination that the voltage-boosted input signal is less than the threshold. The charge pump circuit includes bandgap reference generator configured to receive the voltage-boosted input signal and output, based on the voltage-boosted input signal, a voltage reference signal to a device that operates in accordance with the supply voltage.