Patents by Inventor Eric D. Marshall

Eric D. Marshall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9214462
    Abstract: A semiconductor device fabrication process includes forming a plurality of fins upon a semiconductor substrate and forming a plurality of gate stacks upon the semiconductor substrate orthogonal to the plurality of fins, forming fin portions by recessing the plurality of fins and semiconductor substrate adjacent to the plurality of gate stacks, and forming uniform unmerged epitaxy upon the fin portions. A semiconductor device includes the plurality of fins, the plurality of gate stacks, a first semiconductor substrate recess between a first gate stack pair and a second semiconductor recess between a second gate stack pair, and unmerged epitaxy. The plurality of fins each include fin portions and the unmerged epitaxy including a first epitaxy pair contacting fin portions associated with the first gate stack pair and a second epitaxy pair contacting fin portions associated with the second gate stack pair.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: December 15, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Eric D. Marshall, Alexander Reznicek, Benjamen N. Taber
  • Publication number: 20150318281
    Abstract: A semiconductor device fabrication process includes forming a plurality of fins upon a semiconductor substrate and forming a plurality of gate stacks upon the semiconductor substrate orthogonal to the plurality of fins, forming fin portions by recessing the plurality of fins and semiconductor substrate adjacent to the plurality of gate stacks, and forming uniform unmerged epitaxy upon the fin portions. A semiconductor device includes the plurality of fins, the plurality of gate stacks, a first semiconductor substrate recess between a first gate stack pair and a second semiconductor recess between a second gate stack pair, and unmerged epitaxy. The plurality of fins each include fin portions and the unmerged epitaxy including a first epitaxy pair contacting fin portions associated with the first gate stack pair and a second epitaxy pair contacting fin portions associated with the second gate stack pair.
    Type: Application
    Filed: May 1, 2014
    Publication date: November 5, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Eric D. Marshall, Alexander Reznicek, Benjamen N. Taber