Abstract: To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal CKE onto the memory device's CKE input and (2) a power island for driving a clock enable signal CKE_prime onto that same input. To power down the memory controller, the normal-mode output buffer drives signal CKE low, then the power island drives signal CKE_prime low, then the memory controller (except for the power island) is powered down. The power island continues to drive the memory device's CKE input low to ensure that the memory device stays in self-refresh mode while the memory controller is powered substantially off. To resume normal operations, the power module powers up the memory controller, then the normal-mode output buffer drives signal CKE low, then the power island is disabled, then the memory controller resumes normal operations of the memory device.

Abstract: In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.

Abstract: To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal CKE onto the memory device's CKE input and (2) a power island for driving a clock enable signal CKE_prime onto that same input. To power down the memory controller, the normal-mode output buffer drives signal CKE low, then the power island drives signal CKE_prime low, then the memory controller (except for the power island) is powered down. The power island continues to drive the memory device's CKE input low to ensure that the memory device stays in self-refresh mode while the memory controller is powered substantially off. To resume normal operations, the power module powers up the memory controller, then the normal-mode output buffer drives signal CKE low, then the power island is disabled, then the memory controller resumes normal operations of the memory device.

Abstract: In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.