Abstract: An adaptive volume controlled radiotelephone system includes a microphone, a loudspeaker, a transceiver, and an adaptive volume control. The microphone generates an output electrical audio signal in response to sound, and the loudspeaker produces sound in response to an input electrical audio signal. The transceiver is responsive to the microphone and transmits radiotelephone communications to a remote party and receives radiotelephone communications from the remote party to generate the input electrical audio signal. The adaptive volume control is responsive to the output electrical audio signal and selects an amplitude of the sound produced by the loudspeaker so that the amplitude of the sound produced by the loudspeaker increases as the amplitude of the sound received at the microphone increases and decreases as the amplitude of the sound received at the microphone decreases.

Abstract: A video signal clamp involves evaluating the difference between the signal level and the desired clamp level during the back porch interval. A correction signal indicates whether the signal level must be increased or decreased to establish the desired clamp level. Generation of the correction signal involves a median filter algorithm. Any required increase or decrease of the signal level occurs continuously throughout each horizontal line interval.

Abstract: A circuit for compressing and expanding video color component data comprises a FIFO line memory and a delay circuit. A timing circuit generates control signals for writing data into the line memory and for reading data from the line memory to compress and expand the data. The delay circuit matches the data compressed or expanded in the FIFO line memory to luminance data which is similarly compressed or expanded. A switching network selectively establishes a first signal path in which the line memory precedes the delay circuit for implementing the data expansion and a second signal path in which the delay circuit precedes the line memory for implementing the data compression. The switching network is controlled according to selected display formats requiring compression or expansion, for example by a microprocessor.

Abstract: The digitized video image data stored in a video RAM in a pix-in-pix television receiver is modified by the addition of digital data from an external computer via a computer interface circuit under control of the pix-in-pix controller. The computer interface circuit is coupled to the internal controller of the television receiver via an external input terminal. The additional digital data received from the external computer may be representative of either text or graphics to be merged into the stored video image.

Abstract: A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator for producing a signal having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit which is reset once every horizontal line. In accordance with another aspect of this invention, the state of the divide-by-K circuit is captured and saved for use in a chroma demodulation apparatus just before it is reset.

Abstract: A divider divides down the output of a high frequency oscillator to generate a master clock signal MCS for the purposes of sampling an incoming composite video signal CVS. A skew measuring circuit latches the current state of the divider at a predetermined edge of every incoming horizontal sync signal pulse IHSSP to provide skew data representative of the timing or phase offset between the clock signal MCS and the incoming horizontal sync signal IHSS at the start of each new line of picture information.

Abstract: A television pix-in-pix system includes a pixel memory for storing one field of pixel intensity values of a television signal. A 1-bit overlay indication signal representative of pixel address locations defining a desired indicia on the TV screen is stored in an associated bit map memory. A digital multiplexor having input terminals coupled for respectively receiving the pixel intensity values and suitable overlay display values, and responsive to the overlay indication signal, provides the overlay display values when the overlay indication signal is a logical one, and provides the pixel intensity values otherwise, thereby generating the desired indicia as a part of the inset image on the TV screen.

Abstract: An apparatus is disclosed for generating a burst-locked, color subcarrier representative signal .phi..sub.sc from a skew-corrected clock signal MCS (which is reset once every horizontal line) and a skew error signal SES (indicative of the once-a-line phase adjustment of the skew-corrected clock signal). In accordance with another feature of the invention, a chroma demodulation apparatus is provided for generating a pair of color difference signals R-Y and B-Y in response to the internally-generated .phi..sub.sc signal.