Abstract: The invention relates to a frequency synthesis device comprising a direct digital synthesis device (22) for producing by calculation a signal oscillating at a determined frequency (Fdds), the calculation being performed by a logic circuit clocked by a clock signal (Sh) having a determined clock frequency (Fh), characterized in that it further comprises transposition means (74) for transposing the signal which oscillates at the determined frequency (Fdds) using the clock frequency signal (Sh), the signal thus transposed being supplied as an output (Sref).

Abstract: The filter is composed of a series of cells (E1-E4) Coupled to each other by coupling capacitors (Cc12, Cc23 and Cc34), each cell forming a resonant circuit composed of at least one inductor (Ip1-Ip4) connected in parallel with at least one variable capacitor (Cp1-Cp4). The coupling capacitors (Cc12, Cc23 and Cc34) are variable capacitors. The filter is substantially symmetrical between its signal input (FI) and its signal output (FO). It finds applications notably for the transmission of channels in the UHF band, where it provides frequency agility.