Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Abstract: In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.

Abstract: A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

Abstract: In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.

Abstract: A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

Abstract: Methods and apparatus to improve addressing of device resources in variable page size environments are described. In one embodiment, an address conversion logic (which may be provided within a chipset in an embodiment) may convert a first address into a second address based on a difference between a first memory page size and the second memory page size. Other embodiments are also disclosed.

Abstract: A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.

Abstract: According to one embodiment of the invention, a method comprises measuring memory access latency for a prefetch cycle associated with a transmission of data from a memory device to a destination device such as a storage device. Hereafter, the prefetch rate is dynamically adjusted based on the measured memory access latency.

Abstract: An embodiment is a method and apparatus to prevent the propagation of an error in a transmission from an I/O processor of a peripheral device to a host in a computer system utilizing a PCI, PCI-X, or PCI Express link.

Abstract: An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor and a switch. The switch may comprise one or more ports capable of being coupled to one or more segments external to the switch. The processor may be capable of issuing to the switch one or more commands indicating, at least in part, one or more protocols via which the one or more ports are to communicate and/or one or more forwarding characteristics of the switch. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A PCI Express switch with ports defined to begin operation as upstream ports, and configured to perform a link training that determines when one port is connected to an upstream device and directs the other ports to operate as downstream ports.

Abstract: An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor and a switch. The switch may include at least one port capable of being coupled to at least one external communication link. The processor may be capable of issuing a request to the switch to request that the switch block forwarding via the at least one port of a command received by the switch. The switch may be capable of issuing to an issuer of the command, in response at least in part to receipt by the switch of the command, a response indicating absence of the at least one port from the switch. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: Methods and apparatuses for programming identifications of a peripheral device are described herein. According to one embodiment, the exemplary method includes programming, based on predefined data, one or more fields of configuration registers of a peripheral device in response to a configuration cycle of a data processing system, the one or more fields of the configuration registers including at least one identification register for identifying the peripheral device. Other methods and apparatuses are also described.