Abstract: The invention provides a device including a binary pulse input signal converter, the output of which is connected to a counter and to a delay line that includes a plurality of delay elements. The counter and the delay line also receive a clock signal as an input. The delay line is combined with a sampler and analog memory that includes a plurality of storage cells that receive the input signal as input. Each element of the a delay line includes an output connected to a corresponding storage cell of the analog so as to sequentially control the sampling and storage of the input signal in the storage cells.

Abstract: The invention provides a device including a binary pulse input signal converter, the output of which is connected to a counter and to a delay line that includes a plurality of delay elements. The counter and the delay line also receive a clock signal as an input. The delay line is combined with a sampler and analog memory that includes a plurality of storage cells that receive the input signal as input. Each element of the a delay line includes an output connected to a corresponding storage cell of the analog so as to sequentially control the sampling and storage of the input signal in the storage cells.

Abstract: The invention provides an analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator (101), a clock (102), a digital counter (103) timed by the clock (102), and at least one channel (101, . . . , 10i, . . . , 10n) for data processing, the or each channel comprising a comparator (201, . . . , 20i, . . . , 20n) having an input connected to the ramp generator (101) and the output of which causes for each conversion cycle the storage of the current counter value as a coarse conversion data. According to the present invention, the or each channel (101, . . . , 10i, . . . , 10n) further comprises a delay-chain time interpolator (401, . . . , 40i, . . . , 40n, 501, . . . , 50i, . . .

Abstract: The invention provides an analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator (101), a clock (102), a digital counter (103) timed by the clock (102), and at least one channel (101, . . . , 10i, . . . , 10n) for data processing, the or each channel comprising a comparator (201, . . . , 20i, . . . , 20n) having an input connected to the ramp generator (101) and the output of which causes for each conversion cycle the storage of the current counter value as a coarse conversion data. According to the present invention, the or each channel (101, . . . , 10i, . . . , 10n) further comprises a delay-chain time interpolator (401, . . . , 40i, . . . , 40n, 501, . . . , 50i, . . .

Abstract: An analog sampler for continuous recording and read-out of analog data carried by a bus comprises an array of recording cells aranged in L rows and C columns. Each cell has an analog input coupled to the write bus and an analog output coupled to a read bus. The cells of a column are recorded sequentially, whereas the cells of another column already recorded are read-out simultaneously. A constant number of columns separates the write column from the read column. The system is looped so that writing and read-out go on indefinitely in a continuous way.

Abstract: An analog sampler (1) for continuous recording and read-out of analog data carried by a bus (5) comprises an array (10) of recording cells (2) arranged in L rows (13) and C columns (12). Each cell (2) has an analog input (3) coupled to the write bus (5) and an analog output (103) coupled to a read bus (4) through commutation means (21, 25) having respectively a control digital input (23, 26). The cells of a column are recorded sequentially, whereas the cells of another column already recorded are read-out simultaneously. A constant number of columns separates the write column from the read column. The system is looped so that writing and read-out go on indefinitely in a continuous way.

Abstract: An analog sampler for recording analog data carried by a bus includes an array of recording cells arranged in rows and columns. Each cell has an analog input coupled to the bus by a switch having a controlling digital input. A delay line is associated with each column, coupled to a shift register. Successive outputs of the line are coupled to each of the digital inputs of the cells of the column such that at any moment there is no more than one switch of a single recording switch. The signal is thus not disrupted by noise.

Abstract: An analog sampler (1) for recording analog data carried by a bus (5) comprises an array (10) of recording cells (2) arranged in rows (13) and columns (12). Each cell (2) has an analog input (3) coupled to the bus (5) by means of a switch (21a) having a controlling digital input (23).