Patents by Inventor Eric DeLano
Eric DeLano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10725919Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.Type: GrantFiled: April 8, 2018Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric Delano
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Patent number: 10725920Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.Type: GrantFiled: April 8, 2018Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric Delano
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Patent number: 10705960Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.Type: GrantFiled: April 8, 2018Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric DeLano
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Patent number: 10073779Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.Type: GrantFiled: December 28, 2012Date of Patent: September 11, 2018Assignee: Intel CorporationInventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric Delano
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Publication number: 20180225213Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.Type: ApplicationFiled: April 8, 2018Publication date: August 9, 2018Inventors: Herbert H. HUM, Brinda GANESH, James R. VASH, Ganesh KUMAR, Leena K. PUTHIYEDATH, Scott J. ERLANGER, Eric J. DEHAEMER, Adrian C. MOGA, Michelle M. SEBOT, Richard L. CARLSON, David BUBIEN, Eric DELANO
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Publication number: 20180225211Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.Type: ApplicationFiled: April 8, 2018Publication date: August 9, 2018Inventors: Herbert H. HUM, Brinda GANESH, James R. VASH, Ganesh KUMAR, Leena K. PUTHIYEDATH, Scott J. ERLANGER, Eric J. DEHAEMER, Adrian C. MOGA, Michelle M. SEBOT, Richard L. CARLSON, David Bubien, Eric Delano
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Publication number: 20180225212Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.Type: ApplicationFiled: April 8, 2018Publication date: August 9, 2018Inventors: Herbert H. HUM, Brinda GANESH, James R. VASH, Ganesh KUMAR, Leena K. PUTHIYEDATH, Scott J. ERLANGER, Eric J. DEHAEMER, Adrian C. MOGA, Michelle M. SEBOT, Richard L. CARLSON, David BUBIEN, Eric DELANO
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Patent number: 9792212Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.Type: GrantFiled: September 12, 2014Date of Patent: October 17, 2017Assignee: Intel CorporationInventors: Yen-Cheng Liu, Aamer Jaleel, Bongjin Jung, Zeshan A. Chishti, Adrian C. Moga, Eric Delano, Ren Wang
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Publication number: 20160077970Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Yen-Cheng Liu, Aamer Jaleel, Bongjin Jung, Zeshan A. Chishti, Adrian C. Moga, Eric Delano, Ren Wang
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Patent number: 9183144Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.Type: GrantFiled: December 14, 2012Date of Patent: November 10, 2015Assignee: Intel CorporationInventors: Ren Wang, Ahmad Samih, Eric Delano, Pinkesh J. Shah, Zeshan A. Chishti, Christian Maciocco, Tsung-Yuan Charlie Tai
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Patent number: 9176875Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.Type: GrantFiled: March 5, 2013Date of Patent: November 3, 2015Assignee: Intel CorporationInventors: Ren Wang, Ahmad Samih, Eric Delano, Pinkesh J. Shah, Zeshan A. Chishti, Christian Maciocco, Tsung-Yuan Charlie Tai
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Patent number: 8799586Abstract: Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.Type: GrantFiled: September 30, 2009Date of Patent: August 5, 2014Assignee: Intel CorporationInventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
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Patent number: 8782347Abstract: In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.Type: GrantFiled: June 26, 2009Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric DeLano, Gregory S. Averill
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Publication number: 20140189239Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric Delano
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Publication number: 20140173207Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Inventors: Ren Wang, Ahmad Samih, Eric Delano, Pinkesh J. Shah, Zeshan A. Chishti, Christian Maciocco, Tsung-Yuan Charlie Tai
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Publication number: 20140173206Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.Type: ApplicationFiled: March 5, 2013Publication date: June 19, 2014Inventors: Ren Wang, Ahmad Samih, Eric Delano, Pinkesh J. Shah, Zeshan A. Chishti, Christian Maciocco, Tsung-Yuan Charlie Tai
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Patent number: 8327228Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.Type: GrantFiled: September 30, 2009Date of Patent: December 4, 2012Assignee: Intel CorporationInventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
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Patent number: 8327113Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: September 23, 2008Date of Patent: December 4, 2012Assignee: Intel CorporationInventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas
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Patent number: 8171121Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: September 23, 2008Date of Patent: May 1, 2012Assignee: Intel CorporationInventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas
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Publication number: 20110078492Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill