Abstract: An application server has a custodian application running thereon. The custodian application instantiates a cryptographic microservice. The cryptographic microservice application builds a white-box cryptographic enclave. The custodian application transmits a request for an authorization grant to an authentication computing system. In response, the authentication computing system returns the authorization grant. The custodian application transmits the authorization grant to the cryptographic microservice application. The cryptographic microservice application transmits the authorization grant to the authentication computing system and then receives a digitally signed certificate therefrom. The cryptographic microservice application receives a data encryption key from the custodian application. The cryptographic microservice application transmits a request to the authentication computing system.

Abstract: An application server has a custodian application running thereon. The custodian application instantiates a cryptographic microservice. The custodian application transmits a first request message to a centralized KMS requesting a data encryption key. In response, the centralized KMS returns the data encryption key. The custodian application transmits a second request message to the cryptographic microservice application. The second request message includes a request for a wrapping certificate from the cryptographic microservice application. The custodian application receives the wrapping certificate. The custodian application transmits a third request message to the centralized KMS. The third request message includes the data encryption key encrypted via the master-level tenant key and the wrapping certificate. The custodian application also receives the data encryption key encrypted via the wrapping certificate and transmits it to the cryptographic microservice application.

Abstract: An application server has a custodian application running thereon. The custodian application instantiates a cryptographic microservice. The custodian application transmits a request message to a centralized KMS requesting a data encryption key. In response, the centralized KMS returns the data encryption key. The custodian application transmits the authorization grant request to the centralized KMS and receives the authorization grant and encrypted data encryption key in return. The custodian application transmits the authorization grant and encrypted data encryption key to the cryptographic microservice application. The cryptographic microservice application transmits the authorization grant and encrypted data encryption key to the centralized KMS and receives the decrypted data encryption key in return.

Abstract: An application server has a custodian application running thereon. The server receives a command to instantiate a cryptographic microservice application on the application server. In response, the server instantiates the cryptographic microservice application. The cryptographic microservice application builds a secure enclave on the application server and, within the secure enclave, a cryptogram that represents a virtual fingerprint of the cryptographic microservice application. The server transmits the cryptogram to an authentication computing system. The server receives a digitally signed certificate from the authentication computing system and a data encryption key encrypted with a master tenant key from the custodian application. The server transmits a request to the authentication computing system. The request includes the digitally signed certificate, the data encryption key, and a request to decrypt the data encryption key.

Abstract: Translation of boot code read request commands from an on-board processor of a system on a chip (SoC) from a bus protocol (e.g., advanced high-performance bus (AHB) protocol) into a sequence of commands understandable by a serial interface of the SoC to read boot code from an off-board (e.g., flash or other non-volatile) memory device. The serial interface of the memory device may include a relatively low pin count (e.g., 5 pins) and boot code of the memory device may be modified after tape-out of the SoC free of necessitating a subsequent tape-out of the SoC.

Abstract: An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.

Abstract: An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.

Abstract: Translation of boot code read request commands from an on-board processor of a system on a chip (SoC) from a bus protocol (e.g., advanced high-performance bus (AHB) protocol) into a sequence of commands understandable by a serial interface of the SoC to read boot code from an off-board (e.g., flash or other non-volatile) memory device. The serial interface of the memory device may include a relatively low pin count (e.g., 5 pins) and boot code of the memory device may be modified after tape-out of the SoC free of necessitating a subsequent tape-out of the SoC.

Abstract: A video processing device (150) includes a bitstream accelerator module (106) and a video processing engine (108). The bitstream accelerator module (106) has an input for receiving a stream of encoded video data, and an output adapted to be coupled to a memory (112) for storing partially decoded video data. The bitstream accelerator module (106) partially decodes the stream of encoded video data according to a selected one of a plurality of video formats to provide the partially decoded video data. The video processing engine (108) has input adapted to be coupled to the memory (112) for reading the partially decoded video data, and an output for providing decoded video data.

Abstract: A video processing device (150) includes a bitstream accelerator module (106) and a video processing engine (108). The bitstream accelerator module (106) has an input for receiving a stream of encoded video data, and an output adapted to be coupled to a memory (112) for storing partially decoded video data. The bitstream accelerator module (106) partially decodes the stream of encoded video data according to a selected one of a plurality of video formats to provide the partially decoded video data. The video processing engine (108) has input adapted to be coupled to the memory (112) for reading the partially decoded video data, and an output for providing decoded video data.