Abstract: The disclosed device includes a physical register file (PRF) in a stacked die configuration. Part of the PRF can be implemented in a first die, and another part of the PRF can be implemented in a second die stacked over the first die. The stacked dies can have a similar layout to allow a simplified addressing scheme for accessing the dies of the PRF. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A disclosed method for integer-to-floating-point data transfers includes intercepting, by a scheduler of a register file, a unit of register data from an external computing resource. The method also includes sorting, by the scheduler, the unit of register data into a first-in, first-out queue. Additionally, the method includes selecting, by the scheduler, a port of the register file based on a review of existing data pipelines to the register file. Furthermore, the method includes injecting, by the scheduler, the unit of register data into a data pipeline of the selected port, wherein the unit of register data is held in the first-in, first-out queue until previous register data is processed. Various other methods, devices, and systems are also disclosed.

Abstract: An integrated circuit that performs computations according to an out-of-order execution scheduling scheme can include a first computing region and a second computing region. Such an integrated circuit can also include (i) a first retirement register that stores results of computations performed by the first computing region, and (ii) a second retirement register, physically disposed in proximity to the second computing region, that stores results of computations performed by the second computing region. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A disclosed system includes a physical processor with a scheduler circuit. The scheduler circuit can be configured to: (1) pre-pick, from a set of delayed broadcast scheduler entries, a pre-picked set of scheduler entries that have each met a threshold cycle time, (2) pick for execution, from a set of ready scheduler entries, a picked ready scheduler entry that has met a source dependence cycle time, the set of ready scheduler entries including (A) a set of scheduler entries that have each met the source dependence cycle time, and (B) the pre-picked set of scheduler entries, and (3) delay a broadcast of a scheduler update to the set of delayed broadcast scheduler entries.

Abstract: A cell deactivation device includes a cell deactivation container. The cell deactivation container includes a plurality of microfluidic channels, a lid covering the plurality of microfluidic channels, the lid having a thickness of less than about 150 microns, and a distribution manifold configured to distribute a fluid to the plurality of microfluidic channels. The cell deactivation device further includes an irradiation source configured to generate an electron beam and transmit the electron beam through the lid of the cell deactivation container and into a fluid passing through the plurality of microfluidic channels.

Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.

Abstract: Methods, systems, and apparatuses provide support for allowing thread forward progress in a processing system and that improves quality of service. One system includes a processor; a bus coupled to the processor; a memory coupled to the processor via the bus; and a floating point unit coupled to the processor via the bus, wherein floating point unit comprises hardware control logic operative to: store for each thread, by a scheduler of the floating point unit, a counter; increase, by the scheduler, a value of the counter for each thread corresponding to a thread when at least one source ready operation exist for the thread; compare, by the scheduler, the value of the counter to a predetermined threshold; and make other threads ineligible to be picked by the scheduler when the counter is greater than or equal to the predetermined threshold.

Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.

Abstract: A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.

Abstract: An integrated circuit includes a vector data processing unit that employs a cross-lane shuffle unit including multiplexing logic that programmably shuffles packed source lane values, each corresponding to one of a plurality of vector lanes, to different output vector result lane positions over multiple cycles. In certain implementations, in a first cycle, control logic in the cross-shuffle unit controls the multiplexing logic to select source lane values to be placed in a first group of output vector result lane positions for a vector result register; and in at least a second cycle, the same multiplexing logic is reused to select source lane values to be placed in a second group of output vector result lane positions for the vector result register wherein at least one of the selected source lane values is moved to a different result lane position. Associated methods are also presented.

Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A processor includes a register file and control logic that detects multiple different sets of sequential zero bits of a register in the register file, wherein each of the multiple different sets has a bit length that corresponds to a partial instruction width and operates at a first partial instruction width or a second partial instruction width with the register file depending on number of sets of zero bits detected in the register. In certain examples, the control logic causes operating at first instruction width that avoids merging of a first bit length of data in the register and operating at the second instruction width that avoids merging of a second bit length of data in the register. In some examples, a register rename map table incudes multiple zero bits that identify the detected multiple different sets of bits of sequential zeros.

Abstract: Methods, systems, and apparatuses provide support for allowing thread forward progress in a processing system and that improves quality of service. One system includes a processor; a bus coupled to the processor; a memory coupled to the processor via the bus; and a floating point unit coupled to the processor via the bus, wherein floating point unit comprises hardware control logic operative to: store for each thread, by a scheduler of the floating point unit, a counter; increase, by the scheduler, a value of the counter for each thread corresponding to a thread when at least one source ready operation exist for the thread; compare, by the scheduler, the value of the counter to a predetermined threshold; and make other threads ineligible to be picked by the scheduler when the counter is greater than or equal to the predetermined threshold.

Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.

Abstract: In one representative embodiment, an implantable prosthetic device comprises a spacer body portion configured to be disposed between native leaflets of a heart, and an anchor portion configured to secure the native leaflets against the spacer body portion, wherein the prosthetic device is movable between a compressed configuration, in which the spacer body portion is radially compressed and is axially spaced relative to the anchor portion, and an expanded configuration, in which the spacer body portion expands radially outwardly relative to the compressed configuration and overlaps at least a portion of the anchor portion.

Abstract: In one representative embodiment, an implantable prosthetic device comprises a spacer body portion configured to be disposed between native leaflets of a heart, and an anchor portion configured to secure the native leaflets against the spacer body portion, wherein the prosthetic device is movable between a compressed configuration, in which the spacer body portion is radially compressed and is axially spaced relative to the anchor portion, and an expanded configuration, in which the spacer body portion expands radially outwardly relative to the compressed configuration and overlaps at least a portion of the anchor portion.

Abstract: A weather control station receives from a communication network data packets transmitted wirelessly to the network by a mobile platform separated from the control station. The data packets carry images captured by an image sensor aboard the mobile platform and show one or more weather conditions local to the mobile platform. The control station recovers the images from the data packets and processes the recovered images according to one or more weather condition detection algorithms to detect the one or more weather conditions, respectively. The weather station reports the one or more detected weather conditions.

Abstract: The subject invention provides an antibody composition for detecting E6 protein of at least one HPV strain in a sample. The subject antibodies may be used to detect oncogenic HPV E6 proteins in a sample, and the antibodies find use in a variety of diagnostic and therapeutic applications, including methods of diagnosing and treating cancer. Kits for performing the subject methods and containing the subject antibodies are also provided. Also disclosed in the present invention is a method of generating an antibody that specifically binds to amino-terminus of E6 proteins of at least two HPV strains.

Abstract: The subject invention provides an antibody composition for detecting E6 protein of at least one HPV strain in a sample. The subject antibodies may be used to detect oncogenic HPV E6 proteins in a sample, and the antibodies find use in a variety of diagnostic and therapeutic applications, including methods of diagnosing and treating cancer. Kits for performing the subject methods and containing the subject antibodies are also provided. Also disclosed in the present invention is a method of generating an antibody that specifically binds to amino-terminus of E6 proteins of at least two HPV strains.