Abstract: A circuit capable of driving inductive loads below a chip substrate voltage level while minimizing on-chip power dissipation and eliminating parasitic effects. Two negative voltage drive modes are included in the circuit design. The first drive circuit forces a low negative voltage referenced to the circuit output voltage across an inductive load referenced to ground to provide a slow recirculation of the current in the inductive load. The second drive circuit forces a large negative voltage referenced to the circuit output voltage across the inductive load to provide a fast collapse of the inductive load. The switching regulator switches off when the current to the inductive load reaches a first value and switches on when the recirculating current from back e.m.f. reaches a second value. The switching regulator initially provides a higher level of power when first tuned on.