Abstract: A memory controller comprises a system bus interface that connects the MC to a system processor, a system memory interface that connects the MC to a system memory, a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE), read buffer logic, dynamic controls that are used by the read buffer logic, and an MC processor comprising at least one extended prefetch machine (EPM), each corresponding to one of the at least EPRBEs, where the MC processor is configured to allocate and deallocate EPRBEs and RBEs according to an allocation method using the dynamic controls.

Abstract: A memory controller comprises a system bus interface that connects the MC to a system processor, a system memory interface that connects the MC to a system memory, a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE), read buffer logic, dynamic controls that are used by the read buffer logic, and an MC processor comprising at least one extended prefetch machine (EPM), each corresponding to one of the at least EPRBEs, where the MC processor is configured to allocate and deallocate EPRBEs and RBEs according to an allocation method using the dynamic controls.

Abstract: In response to receipt by a first coherency domain of a memory access request originating from a master in a second coherency domain and excluding from its scope a third coherency domain, coherence participants in the first coherency domain provide partial responses, and one of the coherence participants speculatively provides, to the master, data from a target memory block. The data includes a memory domain indicator indicating whether the memory block is cached, if at all, only within the first coherency domain. Based on the partial responses a combined response is generated representing a systemwide coherence response to the memory access request. In response to the combined response indicating success and the memory domain indicator indicating that a valid copy of the memory block may be cached outside the first coherence domain, the master discards the speculatively provided data and reissues the memory access request with a larger broadcast scope.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: A data processing system includes first and second coherency domains and employs a snoop-based coherence protocol. In response to receipt by the first coherency domain of a memory access request originating from a master in the second coherency domain, a plurality of coherence participants in the first coherency domain provides partial responses for the memory access request to an early combined response generator. Based on the partial responses, the early combined response generator generates and transmits, to a memory controller of a system memory in the first coherency domain, an early combined response of only the first coherency domain. Based on the early combined response, the memory controller transmits, to the master prior to receipt by the memory controller of a systemwide combined response for the memory access request, data associated with a target memory address and/or coherence permission for the target memory address.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: In response to receipt by a first coherency domain of a memory access request originating from a master in a second coherency domain and excluding from its scope a third coherency domain, coherence participants in the first coherency domain provide partial responses, and one of the coherence participants speculatively provides, to the master, data from a target memory block. The data includes a memory domain indicator indicating whether the memory block is cached, if at all, only within the first coherency domain. Based on the partial responses a combined response is generated representing a systemwide coherence response to the memory access request. In response to the combined response indicating success and the memory domain indicator indicating that a valid copy of the memory block may be cached outside the first coherence domain, the master discards the speculatively provided data and reissues the memory access request with a larger broadcast scope.

Abstract: A data processing system includes first and second coherency domains and employs a snoop-based coherence protocol. In response to receipt by the first coherency domain of a memory access request originating from a master in the second coherency domain, a plurality of coherence participants in the first coherency domain provides partial responses for the memory access request to an early combined response generator. Based on the partial responses, the early combined response generator generates and transmits, to a memory controller of a system memory in the first coherency domain, an early combined response of only the first coherency domain. Based on the early combined response, the memory controller transmits, to the master prior to receipt by the memory controller of a systemwide combined response for the memory access request, data associated with a target memory address and/or coherence permission for the target memory address.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Abstract: A memory system comprises memory devices coupled to a memory controller via a memory interface bus, the memory controller for receiving one or more memory requests via an interconnect. The memory controller tracks utilization of the memory interface bus for reads from the memory devices for a selection of the one or more memory requests during a time window. The memory controller, responsive to detecting utilization of the memory interface bus for reads during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of data to be accessed from the memory devices by at least one read operation, the reduced data size selected from among at least two read data size options for the at least one read operation of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Abstract: Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

Abstract: Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

Abstract: In a data processing system, a memory subsystem detects whether or not at least one potentially transient condition is present that would prevent timely servicing of one or more memory access requests directed to the associated system memory. In response to detecting at least one such potentially transient condition, the memory system identifies a first read request affected by the at least one potentially transient condition. In response to identifying the read request, the memory subsystem signals to a request source to issue a second read request for the same target address by transmitting to the request source dummy data and a data error indicator.