Patents by Inventor Eric Enderton

Eric Enderton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170132834
    Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 11, 2017
    Inventors: Yong HE, Eric B. LUM, Eric ENDERTON, Henry Packard MORETON, Kayvon FATAHALIAN
  • Patent number: 9552667
    Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: January 24, 2017
    Assignee: NVIDIA Corporation
    Inventors: Yong He, Eric B. Lum, Eric Enderton, Henry Packard Moreton, Kayvon Fatahalian
  • Publication number: 20150170408
    Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Yong HE, Eric B. LUM, Eric ENDERTON, Henry Packard MORETON, Kayvon FATAHALIAN
  • Publication number: 20150170409
    Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Yong HE, Eric B. LUM, Eric ENDERTON, Henry Packard MORETON, Kayvon FATAHALIAN
  • Publication number: 20140267265
    Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a first graphics primitive intersects a voxel and calculating a first set of coefficients associated with a first plane defined by the intersection of the first graphics primitive and the voxel. The technique further involves determining that a second graphics primitive intersects the voxel and calculating a second set of coefficients associated with a second plane defined by the intersection of the second graphics primitive and the voxel. The technique further involves calculating a third set of coefficients associated with a third surface based on the first set of coefficients and the second set of coefficients. The technique further involves calculating at least one of an amount of the voxel that is located on the back side of the third surface and an occlusion value based on the third set of coefficients.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Cyril CRASSIN, Yury Y. URALSKY, Eric ENDERTON, Eric B. LUM, Jerome F. DULUK, JR., Henry Packard MORETON, David LUEBKE
  • Publication number: 20140267264
    Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves identifying a voxel that is intersected by a first graphics primitive that has a front side and a back side and selecting a plurality of sample points within the voxel. The technique further involves determining, for each sample point included in the plurality of sample points, whether the sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive. Finally, the technique involves storing, for at least a first sample point included in the plurality of sample points, a first result in a voxel mask reflecting whether the first sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Cyril CRASSIN, Yury Y. URALSKY, Eric ENDERTON, Eric B. LUM, Jerome F. DULUK, JR., Henry Packard MORETON, David LUEBKE
  • Publication number: 20140267266
    Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a voxel is intersected by a first graphics primitive that has a front side and a back side and selecting one or more reference points within the voxel. The technique further involves, for each reference point, determining a distance from the reference point to the first graphics primitive and storing a first scalar value in an array based on the distance. The sign of the first scalar value reflects whether the reference point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Cyril CRASSIN, Yury Y. URALSKY, Eric ENDERTON, Eric B. LUM, Jerome F. DULUK, JR., Henry Packard MORETON, David LUEBKE
  • Publication number: 20060059494
    Abstract: Embodiments of methods, apparatuses, devices, and/or systems for load balancing two processors, such as for graphics and/or video processing, for example, are described.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 16, 2006
    Inventors: Daniel Wexler, Larry Gritz, Eric Enderton, Cass Everitt