Abstract: In various examples, optimized cluster templates (e.g., template triblock data, template CLASes or some portion thereof such as template range data, etc.) are precomputed for various patterns of triangle clusters (e.g., regular grids and/or irregular meshes of various edge resolutions) and corresponding compression levels. For example, optimized range assignments may be computed by iteratively generating candidate range assignments using different strategies, evaluating each range assignment using a designated metric (e.g., a cost that estimates, models, approximates, or otherwise quantifies the anticipated time cost of traversal), and tracking the best (e.g., optimized) range assignment (or top N) for each optimized triblock layout. As such, a range assignment may be iteratively optimized for each supported pattern of triangles and corresponding compression level, and may be used to generate a corresponding cluster template.

Abstract: In various examples, a device (e.g., a GPU) may be associated with an application programming interface (API) which an application on a host (e.g., a CPU) may use to manage or control generation of bounding volume hierarchy (BVH) subtrees over clusters of triangles using precomputed cluster templates. For example, the application may issue a first type of API call that identifies a supported pattern of triangles, and the API may return an identifier for a set of associated cluster templates and an associated memory size. As such, the application may allocate memory and issue a second type of API call that identifies the cluster vertices, cluster templates, and location of the allocated memory, and the device may use an applicable cluster template to build a BVH-subtree over the cluster in the allocated memory.

Abstract: In various examples, optimized cluster templates (e.g., template triblock data, template CLASes or some portion thereof such as template range data, etc.) are precomputed for various patterns of triangle clusters (e.g., regular grids and/or irregular meshes of various edge resolutions) and corresponding compression levels. For example, optimized triblock layouts may be computed for triangle patterns with designated parameters by iteratively generating candidate triblock layouts using different strategies, evaluating each candidate triblock layout using a designated metric (e.g., minimizing the number of triblocks used, rotating triblock patterns to a variety of angles and averaging their axis-aligned bounding box (AABB) areas), and tracking the best (e.g., optimized) triblock layout (or top N) for each pattern. As such, a triblock layout may be iteratively optimized for each supported pattern of triangles and corresponding compression level, and may be used to generate a corresponding cluster template.

Abstract: In various examples, a supported pattern of triangles may be associated with multiple cluster templates that represent optimized triblock layouts with different levels of compression. In some embodiments, an application running on a host (e.g., a CPU) may specify an applicable compression level for a cluster of triangles or a device (e.g., a GPU) may identify one (e.g., by inspecting the vertex positions on the fly). As such, the device may look up a set of cluster templates associated with a specified pattern of triangles, identify the cluster template associated with the applicable compression level, copy that cluster template into allocated memory for the cluster, copy or transcode the vertex positions in the cluster into a precomputed triblock layout represented by the cluster template, and build a bounding volume hierarchy subtree over the cluster of triangles using a precomputed range assignment represented by the cluster template.

Abstract: Linear-Swept Sphere (LSS) primitives alongside hardware linear curve intersection testing and traversal logic allow traversal of curves directly within a hardware ray tracer. The introduction of the LSS primitive block, LSS primitive ranges, ray-LSS intersection testing, and LSS fetch removes the requirement that curve traversal utilize ray tracer item-ranges for traversal of curve primitives within a BVH and ray-curve intersection testing through software intersection shaders. Definition of an LSS primitive supports enablement of a single LSS endcap, query and return of the ray-LSS exit hit point, and degenerate-shell LSS intersection testing.

Abstract: To improve the efficiency of bounding volumes in a hardware based ray tracer, we employ a sheared axis-aligned bounding box to approximate an oriented bounding box typically defined by rotations. To achieve this, the bounding volume hierarchy builder shears an axis-aligned box to fit tightly around its enclosed oriented geometry in top level or bottom level space, then computes the inverse shear transform. The bounds are still stored as axis-aligned boxes in memory, now defined in the new sheared coordinate system, along with the derived parameters to transform a ray into the sheared coordinate system before testing intersection with the boxes. The ray-bounding volume intersection test is performed as usual, just in the new sheared coordinate system.

Abstract: To improve the efficiency of bounding volumes in a hardware based ray tracer, we employ a sheared axis-aligned bounding box to approximate an oriented bounding box typically defined by rotations. To achieve this, the bounding volume hierarchy builder shears an axis-aligned box to fit tightly around its enclosed oriented geometry in top level or bottom level space, then computes the inverse shear transform. The bounds are still stored as axis-aligned boxes in memory, now defined in the new sheared coordinate system, along with the derived parameters to transform a ray into the sheared coordinate system before testing intersection with the boxes. The ray-bounding volume intersection test is performed as usual, just in the new sheared coordinate system.

Abstract: To improve the efficiency of bounding volumes in a hardware based ray tracer, we employ a sheared axis-aligned bounding box to approximate an oriented bounding box typically defined by rotations. To achieve this, the bounding volume hierarchy builder shears an axis-aligned box to fit tightly around its enclosed oriented geometry in top level or bottom level space, then computes the inverse shear transform. The bounds are still stored as axis-aligned boxes in memory, now defined in the new sheared coordinate system, along with the derived parameters to transform a ray into the sheared coordinate system before testing intersection with the boxes. The ray-bounding volume intersection test is performed as usual, just in the new sheared coordinate system.

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves identifying a voxel that is intersected by a first graphics primitive that has a front side and a back side and selecting a plurality of sample points within the voxel. The technique further involves determining, for each sample point included in the plurality of sample points, whether the sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive. Finally, the technique involves storing, for at least a first sample point included in the plurality of sample points, a first result in a voxel mask reflecting whether the first sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive.

Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a voxel is intersected by a first graphics primitive that has a front side and a back side and selecting one or more reference points within the voxel. The technique further involves, for each reference point, determining a distance from the reference point to the first graphics primitive and storing a first scalar value in an array based on the distance. The sign of the first scalar value reflects whether the reference point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive.

Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a first graphics primitive intersects a voxel and calculating a first set of coefficients associated with a first plane defined by the intersection of the first graphics primitive and the voxel. The technique further involves determining that a second graphics primitive intersects the voxel and calculating a second set of coefficients associated with a second plane defined by the intersection of the second graphics primitive and the voxel. The technique further involves calculating a third set of coefficients associated with a third surface based on the first set of coefficients and the second set of coefficients. The technique further involves calculating at least one of an amount of the voxel that is located on the back side of the third surface and an occlusion value based on the third set of coefficients.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for load balancing two processors, such as for graphics and/or video processing, for example, are described.