Patents by Inventor Eric Eugene Graf

Eric Eugene Graf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6760868
    Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: July 6, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel P. Drogichen, Eric Eugene Graf, Douglas B. Meyer
  • Patent number: 6571360
    Abstract: A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: May 27, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel P. Drogichen, Eric Eugene Graf, Don Kane, Douglas B. Meyer, Andrew E. Phelps, Patricia Shanahan, Steven F. Weiss
  • Publication number: 20020152421
    Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.
    Type: Application
    Filed: June 13, 2002
    Publication date: October 17, 2002
    Applicant: Sun Microsystems, Inc.
    Inventors: Daniel P. Drogichen, Eric Eugene Graf, Douglas B. Meyer
  • Patent number: 6425094
    Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: July 23, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel P. Drogichen, Eric Eugene Graf, Douglas B. Meyer