Patents by Inventor Eric Eugene Retter
Eric Eugene Retter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7707452Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.Type: GrantFiled: June 9, 2008Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Edgar Rolando Cordero, James Stephen Fields, Jr., Kevin Charles Gower, Eric Eugene Retter, Scott Barnett Swaney
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Patent number: 7493456Abstract: A memory controller includes an address queue with address queue locations that may expand to store address commands that point to consecutive locations in memory. In this manner, multiple address commands may combine together in a common expanded address queue location. In one embodiment, each address queue location includes a main information portion and a supplemental information portion. The supplemental information portion is smaller than the main information portion. The main information portion stores the target address information of a first address command. When the address queue receives an address command with a target address that is consecutive to the target address of the first command, then the supplemental address portion stores a subset of the target address of the second command.Type: GrantFiled: October 13, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Mark Andrew Brittain, Warren Edward Maule, Eric Eugene Retter
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Publication number: 20080270821Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.Type: ApplicationFiled: June 9, 2008Publication date: October 30, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORP.Inventors: Edgar Rolando Cordero, James Stephen Fields, Kevin Charles Gower, Eric Eugene Retter, Scott Barnett Swaney
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Patent number: 7421598Abstract: A method and system for enabling directed temperature/power management at the DIMM-level and/or DRAM-level utilizing intelligent scheduling of memory access operations received at the memory controller. Hot spots within the memory subsystem, caused by operating the DIMMs/DRAMs above predetermined/preset threshold power/temperature values for operating a DIMM and/or a DRAM, are avoided/controlled by logic within the memory controller. The memory controller logic throttles the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on feedback data received from the specific DIMM/DRAM reaching the preset threshold power usage value.Type: GrantFiled: February 9, 2005Date of Patent: September 2, 2008Assignee: International Business Machines CorporationInventors: Mark Andrew Brittain, Edgar Rolando Cordero, James Stephen Fields, Jr., Warren Edward Maule, Eric Eugene Retter
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Patent number: 7409580Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.Type: GrantFiled: February 9, 2005Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Edgar Rolando Cordero, James Stephen Fields, Jr., Kevin Charles Gower, Eric Eugene Retter, Scott Barnett Swaney
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Publication number: 20080091881Abstract: A memory controller includes an address queue with address queue locations that may expand to store address commands that point to consecutive locations in memory. In this manner, multiple address commands may combine together in a common expanded address queue location. In one embodiment, each address queue location includes a main information portion and a supplemental information portion. The supplemental information portion is smaller than the main information portion. The main information portion stores the target address information of a first address command. When the address queue receives an address command with a target address that is consecutive to the target address of the first command, then the supplemental address portion stores a subset of the target address of the second command.Type: ApplicationFiled: October 13, 2006Publication date: April 17, 2008Applicant: IBM CorporationInventors: Mark Andrew Brittain, Warren Edward Maule, Eric Eugene Retter
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Patent number: 5963745Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory elements on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. The architecture uses all the pins for networking. Each chip has eight 16 bit processors, and eight respective 32K memories. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. The scalable chip has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes.Type: GrantFiled: April 27, 1995Date of Patent: October 5, 1999Assignee: International Business Machines CorporationInventors: Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, David Christopher Kuchinski, Billy Jack Knowles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Vincent John Smoral
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Patent number: 5842031Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: June 6, 1995Date of Patent: November 24, 1998Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Donald George Grice, Peter Michael Kogge, David Christoper Kuchinski, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Nicholas Jerome Schoonover, Vincent John Smoral, James Robert Stupp, Paul Amba Wilkinson
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Patent number: 5717943Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: June 5, 1995Date of Patent: February 10, 1998Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Donald George Grice, Peter Michael Kogge, David Christopher Kuchinski, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Nicholas Jerome Schoonover, Vincent John Smoral, James Robert Stupp, Paul Amba Wilkinson
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Patent number: 5710935Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: June 6, 1995Date of Patent: January 20, 1998Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Donald George Grice, Peter Michael Kogge, David Christopher Kuchinski, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Nicholas Jerome Schoonover, Vincent John Smoral, James Robert Stupp, Paul Amba Wilkinson