Patents by Inventor Eric F. Robinson
Eric F. Robinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9645931Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.Type: GrantFiled: March 18, 2016Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Jason A. Cox, M V V Anil Krishna, Eric F. Robinson, Brian M. Rogers
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Publication number: 20160203079Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.Type: ApplicationFiled: March 18, 2016Publication date: July 14, 2016Inventors: JASON A. COX, M V V ANIL KRISHNA, ERIC F. ROBINSON, BRIAN M. ROGERS
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Patent number: 9323675Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.Type: GrantFiled: February 20, 2013Date of Patent: April 26, 2016Assignee: International Business Machines CorporationInventors: Jason A. Cox, M V V Anil Krishna, Eric F. Robinson, Brian M. Rogers
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Patent number: 9292442Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.Type: GrantFiled: July 2, 2013Date of Patent: March 22, 2016Assignee: QUALCOMM IncorporatedInventors: Thomas Philip Speier, Eric F. Robinson, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius, James Norris Dieffenderfer
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Patent number: 9170962Abstract: A method, system and processing device for retiring data entries held within a store queue (STQ). The STQ of a processor cache is modified to receive and process several types of data entries including: non-synchronized (non-sync), thread of execution synchronized (thread-sync), and all thread of execution synchronized (all-thread-sync). The task of storing data entries, from the STQ out to memory or an input/output device, is modified to increase the effectiveness of the cache. The modified STQ allows non-sync, thread-sync, and all-thread-sync instructions to coexist in the STQ regardless of the thread of execution. Stored data entries, or stores are deterministically selected for retirement, according to the data entry type.Type: GrantFiled: December 21, 2007Date of Patent: October 27, 2015Assignee: International Business Machines CorporationInventor: Eric F. Robinson
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Publication number: 20150074357Abstract: A low latency cache intervention mechanism implements a snoop filter to dynamically select an intervener cache for a cache “hit” in a multiprocessor architecture of a computer system. The selection of the intervener is based on variables such as latency, topology, frequency, utilization, load, wear balance, and/or power state of the computer system.Type: ApplicationFiled: March 3, 2014Publication date: March 12, 2015Applicant: QUALCOMM IncorporatedInventors: Joseph G. MCDONALD, Jaya Prakash Subramaniam GANASAN, Thomas Philip SPEIER, Eric F. ROBINSON, Jason Lawrence PANAVICH, Thuong Q. TRUONG
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Patent number: 8938588Abstract: Ensuring forward progress of token-required cache operations in a shared cache, including: snooping an instruction to execute a token-required cache operation; determining if a snoop machine is available and if the snoop machine is set to a reservation state; if the snoop machine is available and the snoop machine is in the reservation state, determining whether the instruction to execute the token-required cache operation owns a token or is a joint instruction; if the instruction is a joint instruction, instructing the operation to retry; if the instruction to execute the token-required cache operation owns a token, dispatching a cache controller; determining whether all required cache controllers of relevant compute nodes are available to execute the instruction; executing the instruction if the required cache controllers are available otherwise not executing the instruction.Type: GrantFiled: December 16, 2010Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: Jason A. Cox, Eric F. Robinson, Mark J. Wolski
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Patent number: 8930680Abstract: A method, system and process for retiring data entries held within a store queue (STQ). The STQ of a processor cache is modified to receive and process multiple synchronized groups (sync-groups). Sync groups comprise thread of execution synchronized (thread-sync) entries, all thread of execution synchronized (all-thread-sync) entries, and regular store entries (non-thread-sync and non-all-thread-sync). The task of storing data entries, from the STQ out to memory or an input/output device, is modified to increase the effectiveness of the cache. Sync-groups are created for each thread and tracked within the STQ via a synchronized identification (SID). An entry is eligible for retirement when the entry is within a currently retiring sync-group as identified by the SID.Type: GrantFiled: December 21, 2007Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventor: Eric F. Robinson
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Publication number: 20140310468Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.Type: ApplicationFiled: July 2, 2013Publication date: October 16, 2014Inventors: Thomas Philip Speier, Eric F. Robinson, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius, James Norris Dieffenderfer
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Patent number: 8850095Abstract: A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N2).Type: GrantFiled: February 8, 2011Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Amit Golander, Omer Heymann, Nadav Levison, Eric F. Robinson
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Publication number: 20140237186Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.Type: ApplicationFiled: February 20, 2013Publication date: August 21, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason A. Cox, M V V Anil Krishna, Eric F. Robinson, Brian M. Rogers
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Patent number: 8707449Abstract: Acquiring access to a token controlled system resource, including: receiving, by a token broker, a command that requires access to the token controlled system resource, where the token broker is automated computing machinery for acquiring tokens and distributing the command to the token controlled system resource for execution; identifying, by the token broker, a first need state, the first need state indicating that the token broker requires access to the token controlled system resource to which the token broker does not possess a token; requesting, by the token broker, a configurable number of tokens to gain access to the token controlled system resource, without dispatching an operation handler for executing the command until at least one token is acquired; assigning, by the token broker, an acquired token to the operation handler; and dispatching, by the token broker, the operation handler and its assigned token for executing the command.Type: GrantFiled: December 16, 2010Date of Patent: April 22, 2014Assignee: International Business Machines CorporationInventors: Jason A. Cox, Kevin C. Lin, Eric F. Robinson, Mark J. Wolski
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Patent number: 8671247Abstract: An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.Type: GrantFiled: December 14, 2010Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventors: Jason A. Cox, Kevin C K Lin, Eric F. Robinson, Mark J. Wolski
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Patent number: 8656106Abstract: Methods, apparatuses, and computer program products are disclosed for cache management. Embodiments include receiving, by a cache controller, a request to insert a new cache line into a cache; determining, by the cache controller, whether the new cache line is associated with a forced injection; in response to determining that the new cache line is associated with a forced injection, accepting, by the cache controller, the insertion of the new cache line into the cache; and in response to determining that the new cache line is not associated with a forced injection, determining, by the cache controller, whether to accept the insertion of the new cache line based on a comparison of an address of the new cache line to a predefined range of addresses.Type: GrantFiled: December 16, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Jason A. Cox, Praveen G. Karandikar, Eric F. Robinson, Mark J. Wolski
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Patent number: 8639889Abstract: One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.Type: GrantFiled: January 31, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Jason A. Cox, Robert J. Dorsey, Kevin C K Lin, Eric F. Robinson
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Patent number: 8601193Abstract: Counter registers are shared among multiple threads executing on multiple processor cores. An event within the processor core is selected. A multiplexer in front of each of a number of counters is configured to route the event to a counter. A number of counters are assigned for the event to each of a plurality of threads running for a plurality of applications on a plurality of processor cores, wherein each of the counters includes a thread identifier in the interrupt thread identification field and a processor identifier in the processor identification field. The number of counters is configured to have a number of interrupt thread identification fields and a number of processor identification fields to identify a thread that will receive a number of interrupts.Type: GrantFiled: October 8, 2010Date of Patent: December 3, 2013Assignee: International Business Machines CorporationInventors: Etai Adar, Srinivasan Ramani, Eric F. Robinson, Thuong Q. Truong
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Patent number: 8589922Abstract: A number of hypervisor register fields are set to specify which processor cores are allowed to generate a number of performance events for a particular thread group. A plurality of threads for an application running in the computing environment to a plurality of thread groups are configured by a plurality of thread group fields in a plurality of control registers. A number of counter sets are allowed to count a number of thread group events originating from one of a shared resource and a shared cache are specified by a number of additional hypervisor register fields.Type: GrantFiled: October 8, 2010Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Etai Adar, Srinivasan Ramani, Eric F. Robinson, Thuong Q. Truong
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Patent number: 8489787Abstract: Sampled instruction address registers are shared among multiple threads executing on a plurality of processor cores. Each of a plurality of sampled instruction address registers are assigned to a particular thread running for an application on the plurality of processor cores. Each of the sampled instruction address registers are configured by storing in each of the sampled instruction address registers a thread identification of the particular thread in a thread identification field and a processor identification of a particular processor on which the particular thread is running in a processor identification field.Type: GrantFiled: October 12, 2010Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Etai Adar, Russell D. Hoover, Srinivasan Ramani, Eric F. Robinson, Thuong Q. Truong
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Patent number: 8417851Abstract: In a disclosed example of a method, a requested value of a target register may be specified as a precondition to performing a requested read or write operation. The requested read or write operation may be generated by a requesting device, such as a processor, and sent over a bus to a peripheral device containing the target register. The target register may be polled internally to the peripheral device without generating additional bus traffic between the requesting device and the peripheral device. A ring topology may be used to internally poll the target register and to perform the requested read or write operation when the polled value of the target register equals the requested value.Type: GrantFiled: June 27, 2011Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Etai Adar, Eric F. Robinson, Yossi Shapira
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Patent number: 8386712Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.Type: GrantFiled: May 7, 2008Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers