Patents by Inventor Eric Finley

Eric Finley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11219440
    Abstract: A surgical access system including a tissue distraction assembly and a tissue retraction assembly, both of which may be equipped with one or more electrodes for use in detecting the existence of (and optionally the distance and/or direction to) neural structures before, during, and after the establishment of an operative corridor to a surgical target site.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: January 11, 2022
    Assignee: NuVasive, Inc.
    Inventors: Patrick Miles, Scot Martinelli, Eric Finley, James E. Gharib, Allen Farquhar, Norbert F. Kaula, Jeffrey J. Blewett
  • Patent number: 11213236
    Abstract: A pedicle access system including a cannula, a stylet, and a removable T-handle. The pedicle access system may be used to percutaneously approach the pedicle, initiate pilot hole formation, and conduct a stimulation signal to the target site for the purposes of performing a pedicle integrity assessment during the pilot hole formation. To do this, the cannula and stylet are locked in combination and inserted through an operating corridor to the pedicle target site, using the T-handle to facilitate easy movement and positioning of the cannula/stylet combination. A stimulation signal may be applied during pilot hole formation to conduct the pedicle integrity assessment. In a significant aspect, the T-handle may be detached from the cannula/stylet combination to facilitate the use of various surgical tools as necessary.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: January 4, 2022
    Assignee: NuVasive, Inc.
    Inventors: Thomas Scholl, Albert Kim, Eric Finley, Albert Pothier, Scot Martinelli, Jared Arambula
  • Patent number: 11207132
    Abstract: A method is provided for correcting a curvature or deformity in a patient's spine based on the digitized locations of implanted screws. The method is implemented by a control unit through a GUI to digitize screw locations, accept one or more correction outputs, and generate one or more rod solution outputs shaped to fit at locations distinct from the implanted screw locations.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 28, 2021
    Assignee: NuVasive, Inc.
    Inventors: Robert E. Isaacs, Thomas Scholl, Jeff Barnes, Eric Finley
  • Publication number: 20210398299
    Abstract: Example systems and methods correctly align or register a first image with a second image using user input to identify location(s) of interest in the overlay image. The system can ask a user to select a vertebral level of interest on a screen displaying the baseline and/or the overlay image. Then, the user input can be advantageously to guide subsequent image registration steps. The systems and methods herein may also be used to augment an existing image-recognition algorithm.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 23, 2021
    Inventors: Sean O'Connor, Eric Finley, Kara Robinson
  • Patent number: 11191592
    Abstract: The present invention relates to a system and methods generally aimed at monitoring the angular orientation between two locations within a fluoroscopic image and especially for monitoring the angular orientation between two locations within a fluoroscopic image and a predetermined target angle.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: December 7, 2021
    Assignee: NuVasive, Inc.
    Inventors: Josef Gorek, Eric Finley, Albert C Kim, Jeffrey Barnes, Rick Eis
  • Publication number: 20210298660
    Abstract: A surgical access system including a tissue distraction assembly and a tissue refraction assembly, both of which may be equipped with one or more electrodes for use in detecting the existence of (and optionally the distance and/or direction to) neural structures before, during, and after the establishment of an operative corridor to a surgical target site.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Patrick Miles, Scot Martinelli, Eric Finley
  • Publication number: 20210290216
    Abstract: A surgical access system including a tissue distraction assembly 40 and a tissue retraction assembly 10, both of which may be equipped with one or more electrodes 23 for use in detecting the existence of (and optionally the distance and/or direction to) neural structures before, during, and after the establishment of an operative corridor 15 to a surgical target site. The tissue retraction assembly 10 has a plurality of blades 12, 16, 18 which may be introduced while in a closed configuration, after which point they may be opened to create an operation corridor 15 to the surgical target site, including pivoting at least one blade 12, 16, 18 to expand the operative corridor 15 adjacent to the operative site.
    Type: Application
    Filed: January 29, 2021
    Publication date: September 23, 2021
    Inventors: Scot Martinelli, Jared Arambula, Eric Finley, Patrick Miles
  • Publication number: 20210256654
    Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 19, 2021
    Applicant: Intel Corporation
    Inventors: Altug Koker, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Josh Mastronarde, Naveen Matam, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
  • Patent number: 11064934
    Abstract: A surgical access system including a tissue distraction assembly and a tissue refraction assembly, both of which may be equipped with one or more electrodes for use in detecting the existence of (and optionally the distance and/or direction to) neural structures before, during, and after the establishment of an operative corridor to a surgical target site.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: July 20, 2021
    Assignee: NuVasive, Inc.
    Inventors: Patrick Miles, Scot Martinelli, Eric Finley
  • Publication number: 20210186617
    Abstract: The present invention relates to a system and methods generally aimed at monitoring the angular orientation between two locations within a fluoroscopic image and especially for monitoring the angular orientation between two locations within a fluoroscopic image and a predetermined target angle.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Josef GOREK, Eric FINLEY, Albert C. KIM, Jeffrey BARNES, Rick EIS
  • Publication number: 20210177391
    Abstract: A system for accessing a surgical target site and related methods, involving an initial distraction system for creating an initial distraction corridor, and an assembly capable of distracting from the initial distraction corridor to a secondary distraction corridor and thereafter sequentially receiving a plurality of retractor blades for retracting from the secondary distraction corridor to thereby create an operative corridor to the surgical target site, both of which may be equipped with one or more electrodes for use in detecting the existence of (and optionally the distance and/or direction to) neural structures before, during, and after the establishment of an operative corridor to a surgical target site.
    Type: Application
    Filed: February 15, 2021
    Publication date: June 17, 2021
    Inventors: Patrick Miles, Scot Martinelli, Eric Finley, James E. Gharib, Allen Farquhar, Norbert F. Kaula, Jeffrey J. Blewett
  • Publication number: 20210133913
    Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
    Type: Application
    Filed: October 13, 2020
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker, Josh Mastronarde, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
  • Patent number: 10980524
    Abstract: A system for accessing a surgical target site and related methods, involving an initial distraction system for creating an initial distraction corridor, and an assembly capable of distracting from the initial distraction corridor to a secondary distraction corridor and thereafter sequentially receiving a plurality of retractor blades for retracting from the secondary distraction corridor to thereby create an operative corridor to the surgical target site, both of which may be equipped with one or more electrodes for use in detecting the existence of (and optionally the distance and/or direction to) neural structures before, during, and after the establishment of an operative corridor to a surgical target site.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: April 20, 2021
    Assignee: NuVasive, Inc.
    Inventors: Patrick Miles, Scot Martinelli, Eric Finley, James E. Gharib, Allen Farquhar, Norbert F. Kaula, Jeffrey J. Blewett
  • Patent number: 10983581
    Abstract: Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Altug Koker, Yoav Harel, Kenneth Brand, Chandra Gurram, Eric Finley, Bhushan Borole, Carlos Nava Rodriguez
  • Patent number: 10909652
    Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Altug Koker, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Josh Mastronarde, Naveen Matam, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
  • Patent number: 10803548
    Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker, Josh Mastronarde, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
  • Publication number: 20200320786
    Abstract: A method is disclosed for spinal anatomy segmentation. In one example, the method includes combining a fully convolutional network with a residual neural network. The method also includes training the combined fully convolutional network with the residual neural network from end to end. The method also includes receiving at least one medical image of a spinal anatomy. The method also includes applying the fully convolutional network with the residual neural network to at least one medical image and segmenting at least one vertebral body from the at least one medical image of the spinal anatomy.
    Type: Application
    Filed: April 19, 2020
    Publication date: October 8, 2020
    Inventors: Samuel Kadoury, Eric Finley
  • Publication number: 20200294180
    Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Altug Koker, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Josh Mastronarde, Naveen Matam, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
  • Publication number: 20200294181
    Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker, Josh Mastronarde, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
  • Publication number: 20200289210
    Abstract: Methods are provided for planning, performing, and assessing of surgical correction to the spine during a spinal surgical procedure. These methods are implemented by a control unit through a GUI to digitize screw locations, digitize anatomical reference points, accept one or more correction inputs, and generate one or more rod solution outputs shaped to engage the screws at locations distinct from the originally digitized locations.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Inventors: Thomas Scholl, Robert E. Isaacs, Shannon White, Albert Pothier, Robert German, Eric Finley, James E. Gharib, Mark Peterson