Abstract: Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.

Abstract: Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.

Abstract: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

Abstract: A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.

Abstract: A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.

Abstract: A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The mask contains information that specifies a selected page size and a selected logic mode that can be applied to a compare array in which the specified search is conducted. The compare array is coupled to a data array to which the compare array indicates a result of the search.

Abstract: A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.

Abstract: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.