Abstract: A differential-input flash analog-to-digital converter (ADC) uses digital common-mode rejection wherein the output sequences from two non-differential flash ADCs are differenced and further processed in the digital domain. Each of a pair of non-differential ADCs converts an associated one of two received voltage signals into a digital signal having N quantization levels, a subtractor digitally subtracts the two digital signals to produce a difference signal having 2N quantization levels, and a re-quantizer re-quantizes the difference signal to produce an N-level quantized representation of the difference signal. The flash ADC also effects comparator offset dynamic element matching to reduce the deleterious effects of ADC error resulting from the inevitable non-zero offset voltages of the comparators from which the each flash ADC is constructed.