Patents by Inventor Eric Fonteneau

Eric Fonteneau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device and process for processing a message and sending a LPWAN message
    Patent number: 11974119
    Abstract: A process for processing a received message, where the message includes encrypted data and at least one indicator element, is disclosed. The process includes generating a complete indicator from data stored in the electronic device and from the received indicator element, generating a key from the complete indicator, and decrypting the encrypted data using said key. The disclosure also relates to a corresponding sending process.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: April 30, 2024
    Inventors: Eric Therene, Sébastien Nerot, Anthony Fonteneau
  • Process and electronic decoding circuit for a diphase asynchronous frame whose length is not known in advance, corresponding application, computer programme and storage means
    Patent number: 7564936
    Abstract: A decoding process, by an electronic circuit of a diphase asynchronous frame carried by an encoded data signal and comprising L information bits followed by at least one stop bit. The process comprises a step for automatically detecting the length L in information bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that Lmin?L?Lmax=(Lmin+k), where k is a predetermined whole number greater than or equal to one.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: July 21, 2009
    Assignee: Atmel Nantes SA
    Inventors: Eric Fonteneau, Virginie Klingler
  • Process and electronic decoding circuit for a diphase asynchronous frame whose length is not known in advance, corresponding application, computer programme and storage means
    Publication number: 20050175134
    Abstract: A decoding process, by an electronic circuit of a diphase asynchronous frame carried by an encoded data signal and comprising L information bits followed by at least one stop bit. The process comprises a step for automatically detecting the length L in information bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that Lmin?L?Lmax=(Lmin+k), where k is a predetermined whole number greater than or equal to one.
    Type: Application
    Filed: November 19, 2004
    Publication date: August 11, 2005
    Applicant: ATMEL NANTES SA
    Inventors: Eric Fonteneau, Virginie Klingler