Abstract: Examples described herein provide a computer-implemented method that includes receiving a circuit design and a set of known process, voltage, and temperature (PVT) points for components of the circuit design. The method further includes determining parameter ratios for the set of known PVT points. The method further includes performing a statistical static timing analysis on the circuit design using the set of known PVT points and at least one additional PVT point generated during the statistical static timing analysis. The method further includes performing projections and root sum squaring for possible corners in a parameter space based on a canonical model generated during performing the statistical static timing analysis.

Abstract: Timing constraint auto-creation for integrated circuit testing includes analyzing an integrated circuit design using a first clocking attribute, wherein the first clocking attribute describes a first clock for the integrated circuit design; identifying, based on the analysis and the first clocking attribute, design features of the integrated circuit design necessitating timing constraints; and generating, based on the identified design features, the timing constraints for the static timing analysis of the integrated circuit design.

Abstract: The present disclosure describes systems and methods for performing timing analysis of circuit designs. According to an embodiment, a method includes assigning a timing margin to a non-scan latch of a circuit design and performing a timing analysis on the circuit design using the timing margin for the non-scan latch to produce timing results for the circuit design. The timing results include a slack value. The method also includes calculating a credit based on the slack value and updating the slack value based on the credit.

Abstract: Timing analysis of a digital integrated circuit using intent based timing constraints includes defining a plurality of intent groups for an integrated circuit design. Each intent group is associated with a different clock type of the integrated circuit design. A different timing phase of a plurality of timing phases of one or more clock signals of the integrated circuit design is associated with each intent group. One or more timing constraints is associated with each of the intent groups. A timing result is computed based on propagating the timing phases of each of the intent groups and applying the associated timing constraints from an input to a timing point of the integrated circuit design.

Abstract: Embodiments of the invention are directed to a computer-implemented method of determining timing constraints of a first component-under-design (CUD). The computer-implemented method includes accessing, using a processor, a plurality of timing constraint requirements configured to be placed on the first CUD by one or more second CUDs, wherein each of the plurality of timing constraint requirements is specifically designed for the CUD. The processor is used to perform a comparative analysis of each of the plurality of timing constraints to identify a single timing constraint that satisfies each of the plurality of timing constraints.

Abstract: Embodiments of the invention are directed to a computer-implemented method of determining timing constraints of a first component-under-design (CUD). The computer-implemented method includes accessing, using a processor, a plurality of timing constraint requirements configured to be placed on the first CUD by one or more second CUDs, wherein each of the plurality of timing constraint requirements is specifically designed for the CUD. The processor is used to perform a comparative analysis of each of the plurality of timing constraints to identify a single timing constraint that satisfies each of the plurality of timing constraints.

Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

Abstract: A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.

Abstract: A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.

Abstract: A system and method to perform timing analysis in integrated circuit development involves defining an integrated circuit design as nodes representing components of the integrated circuit design that are interconnected by edges representing wires. Sequentially connected nodes define a path. Statistical variables are defined for a canonical delay model of each node and edge of the integrated circuit design and define a first set of conditions. The method includes performing a statistical static timing analysis to obtain an arrival time at each node as a sum of the canonical delay models for nodes and edges that precede the node in the path of the node, obtaining a projected arrival time at a second set of conditions for the node by scaling the arrival time for the node using scale factors that represent the second set of conditions and using a transformation matrix, and providing the integrated circuit design for fabrication.

Abstract: A system and method to perform timing analysis in integrated circuit development involves defining an integrated circuit design as nodes representing components of the integrated circuit design that are interconnected by edges representing wires. Sequentially connected nodes define a path. Statistical variables are defined for a canonical delay model of each node and edge of the integrated circuit design and define a first set of conditions. The method includes performing a statistical static timing analysis to obtain an arrival time at each node as a sum of the canonical delay models for nodes and edges that precede the node in the path of the node, obtaining a projected arrival time at a second set of conditions for the node by scaling the arrival time for the node using scale factors that represent the second set of conditions and using a transformation matrix, and providing the integrated circuit design for fabrication.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.