Patents by Inventor Eric Fu

Eric Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12542185
    Abstract: A memory device includes a set of memory cells and a control circuit coupled to the set of memory cells. The control circuit is configured to transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level. While the wordline voltage settles at the second wordline voltage level, the control circuit cuts off current to the target memory cell by at least one of temporarily ramping down a bitline voltage from a first bitline voltage level to a second bitline voltage level, temporarily ramping down a select gate voltage from a first select gate voltage level to a second select gate voltage level, and temporarily ramping up a source line voltage from a first source level to a second source level.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: February 3, 2026
    Assignee: Sandisk Technologies, Inc.
    Inventors: Xiang Yang, Eric Fu, Albert Chen, Jonathan Huynh
  • Publication number: 20250378885
    Abstract: A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means is configured to determine ones of the data states for the memory cells of a neighboring word line adjacent to a selected word line in a pre-read. The control means determines an adjusted sense time according to a zone identified for the memory cells of the neighboring word line and the one of the data states targeted for the memory cells of the selected word line and a temperature of the memory apparatus. The control means is also configured to perform reads on the selected word line for each of a plurality of groupings of ones of the data states in a read operation using the adjusted sense time determined for each of the memory cells of the selected word line.
    Type: Application
    Filed: June 6, 2024
    Publication date: December 11, 2025
    Inventors: Albert Chen, Xiang Yang, Jiahui Yuan, Eric Fu
  • Publication number: 20250372178
    Abstract: A non-volatile storage apparatus stores data in the non-volatile memory cells by programming the non-volatile memory cells to a set of data states and reads data stored in the non-volatile memory cells by sensing for a set of read reference levels for the data states. To address data retention issues, including memory cells having the threshold voltages drift over time, one or more of the set of read reference levels are shifted based on sensing the non-volatile memory cells for two different conditions during a single ramping up of a voltage signal applied to the non-volatile memory cells.
    Type: Application
    Filed: June 27, 2024
    Publication date: December 4, 2025
    Applicant: Sandisk Technologies, Inc.
    Inventors: Albert Chen, Eric Fu, Jiahui Yuan, Anirudh Amarnath, Xiang Yang
  • Publication number: 20240420775
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory cells are disposed in memory holes grouped in blocks. A control means is configured to determine an amount of the memory cells of one of the blocks that are programmed during at least one read operation. The control means adjusts at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed. The control means is also configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the plurality of data states in the at least one read operation.
    Type: Application
    Filed: August 4, 2023
    Publication date: December 19, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Albert Chen, Xiang Yang, Eric Fu, Jiahui Fu
  • Publication number: 20240420773
    Abstract: An apparatus comprising a set of memory cells and a control circuit coupled to the set of memory cells is disclosed. The control circuit is configured to: transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level; subsequent to transitioning the wordline voltage to the second wordline voltage level, ramp down a bitline voltage of a bitline associated with the target memory cell from a first bitline voltage level to a second bitline voltage level; and prior to sensing a state of the memory cell, ramp up the bitline voltage from the second bitline voltage level to the first bitline voltage level.
    Type: Application
    Filed: August 3, 2023
    Publication date: December 19, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xiang Yang, Eric Fu, Albert Chen, Jonathan Huynh
  • Patent number: 10389849
    Abstract: A distributed computational system, with local and remote processing components, is configured to provide a user interface of the local component that is stored in the local component but is controlled and updated by the remote component.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: August 20, 2019
    Assignee: HERE Global B.V.
    Inventors: Curtis Allred, Geoffrey Bonser, Eric Fu, Michael Libes
  • Publication number: 20100077362
    Abstract: A distributed computational system, with local and remote processing components, is configured to provide a user interface of the local component that is stored in the local component but is controlled and updated by the remote component.
    Type: Application
    Filed: April 22, 2009
    Publication date: March 25, 2010
    Applicant: Medio Systems, Inc.
    Inventors: Curt Allred, Geoffrey Bonser, Eric Fu, Michael Libes
  • Publication number: 20080016219
    Abstract: A resource request is received at a computer application, wherein the resource request has a resource specification that determines multiple resources for fulfillment. The received resource specification is evaluated, a plurality of computer resources are identified for processing of the resource request in accordance with the evaluated resource specification, and an order of processing the request among the identified computer resources is identified for fulfillment of the resource request. The resource request itself can determine network locations at which the requested resource can be found. In the case of a Web browser user application that is configured to process such a conditional resource request, the request comprises a conditional uniform resource locator (C-URL) that describes one or more network locations at which a single resource may be accessed.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 17, 2008
    Applicant: Medio Systems, Inc.
    Inventors: Michael Libes, Eric Fu