Patents by Inventor Eric G. F. Hochapfel

Eric G. F. Hochapfel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cross function block partitioning and placement of a circuit design onto reconfigurable logic devices
    Patent number: 6658636
    Abstract: A first and a second netlist of a first and a second function block of a circuit design are correspondingly partitioned into at least a first and a second partition, and a third and a fourth partition respectively. The first and third partitions include majorities of the constituting elements of the first and second netlists respectively. The second and fourth partitions include minorities of the constituting elements of the first and second netlists. Placements of the constituting elements of the first and third partitions are correspondingly determined. The second and fourth partitions are merged to form a composite partition, which in turn is partitioned for joint determination of placement of these minority constituting elements of the first and second netlists of the first and second function blocks on logic devices. In one embodiment, the second and fourth partitions operate in the one clock domain, while the first and third partitions operate in one or more other clock domains.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: December 2, 2003
    Inventor: Eric G. F. Hochapfel
  • Cross function block partitioning and placement of a circuit design onto reconfigurable logic devices
    Publication number: 20030009735
    Abstract: A first and a second netlist of a first and a second function block of a circuit design are correspondingly partitioned into at least a first and a second partition, and a third and a fourth partition respectively. The first and third partitions include majorities of the constituting elements of the first and second netlists respectively. The second and fourth partitions include minorities of the constituting elements of the first and second netlists. Placements of the constituting elements of the first and third partitions are correspondingly determined. The second and fourth partitions are merged to form a composite partition, which in turn is partitioned for joint determination of placement of these minority constituting elements of the first and second netlists of the first and second function blocks on logic devices. In one embodiment, the second and fourth partitions operate in the one clock domain, while the first and third partitions operate in one or more other clock domains.
    Type: Application
    Filed: July 9, 2001
    Publication date: January 9, 2003
    Inventor: Eric G.F. Hochapfel