Abstract: A Group III nitride transistor cell is provided that includes a Group III nitride-based body, a source finger, a gate finger, and a drain finger extending substantially parallel to one another and positioned on the Group III nitride-based body, the gate finger being arranged laterally between the source finger and the drain finger and including a p-type Group III nitride finger arranged on the Group III nitride body and a gate metal finger arranged on the p-type Group III nitride finger, and a protection diode. The protection diode is integrated into the Group III nitride transistor cell and operable to conduct current in a reverse direction when the Group III nitride transistor cell is switched off. The protection diode is electrically coupled between the source and drain fingers and is positioned on the Group III nitride body laterally between and spaced apart from the gate finger and the drain finger.

Abstract: A Group III nitride transistor cell is provided that includes a Group III nitride-based body, a source finger, a gate finger, and a drain finger extending substantially parallel to one another and positioned on the Group III nitride-based body, the gate finger being arranged laterally between the source finger and the drain finger and including a p-type Group III nitride finger arranged on the Group III nitride body and a gate metal finger arranged on the p-type Group III nitride finger, and a protection diode. The protection diode is integrated into the Group III nitride transistor cell and operable to conduct current in a reverse direction when the Group III nitride transistor cell is switched off. The protection diode is electrically coupled between the source and drain fingers and is positioned on the Group III nitride body laterally between and spaced apart from the gate finger and the drain finger.

Abstract: In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Abstract: In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Abstract: In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Abstract: A Group III nitride transistor cell is provided that includes a Group III nitride-based body, a source finger, a gate finger, and a drain finger extending substantially parallel to one another and positioned on the Group III nitride-based body, the gate finger being arranged laterally between the source finger and the drain finger and including a p-type Group III nitride finger arranged on the Group III nitride body and a gate metal finger arranged on the p-type Group III nitride finger, and a protection diode. The protection diode is integrated into the Group III nitride transistor cell and operable to conduct current in a reverse direction when the Group III nitride transistor cell is switched off. The protection diode is electrically coupled between the source and drain fingers and is positioned on the Group III nitride body laterally between and spaced apart from the gate finger and the drain finger.

Abstract: In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Abstract: A circuit includes a bridgeless flyback converter having a primary side electromagnetically coupled to a secondary side by a transformer, the primary side being devoid of a diode bridge rectifier, an input capacitor coupled to the primary side of the bridgeless flyback converter, an output capacitor coupled to the secondary side of the bridgeless flyback converter, an EMI (electromagnetic interference) filter coupled between an AC input and the input capacitor, and a compensation stage coupled in parallel with the output capacitor and including a storage capacitor. The input capacitor has a capacitance such that the compensation stage filters the AC mains frequency ripple of the AC input from the secondary side. The compensation stage is configured to store energy in the storage capacitor and regulate the voltage across the output capacitor. The bridgeless flyback converter is configured to regulate the voltage across the storage capacitor.

Abstract: A circuit includes a bridgeless flyback converter having a primary side electromagnetically coupled to a secondary side by a transformer, the primary side being devoid of a diode bridge rectifier, an input capacitor coupled to the primary side of the bridgeless flyback converter, an output capacitor coupled to the secondary side of the bridgeless flyback converter, an EMI (electromagnetic interference) filter coupled between an AC input and the input capacitor, and a compensation stage coupled in parallel with the output capacitor and including a storage capacitor. The input capacitor has a capacitance such that the compensation stage filters the AC mains frequency ripple of the AC input from the secondary side. The compensation stage is configured to store energy in the storage capacitor and regulate the voltage across the output capacitor. The bridgeless flyback converter is configured to regulate the voltage across the storage capacitor.

Abstract: A gas discharge lamp control circuit includes a series circuit formed by first and second AC input terminals, an inductance and first and second lamp terminals. An ignitor circuit is coupled to the series circuit and selectively couples and decouples at least a portion of the inductance in parallel with the first and second AC input terminals to generate a flyback voltage in the inductance.

Abstract: A phase control circuit according to the present invention is configured for connection between and AC source and an AC load. The AC source supplies an AC drive signal having a plurality of sequential positive and negative half cycles. The phase control circuit comprises first and second power switches coupled between the AC source and the AC load. The first power switch conducts current of the AC drive signal after a first phase delay during the positive half cycles. The second power switch conducts current of the AC drive signal after a second phase delay during the negative half cycles. A feedback balance circuit is coupled between the AC load and the first and second power switches. The feedback balance circuit determines a DC current component in the AC load and generates a phase delay correction signal as a function of the DC current component.

Abstract: A control circuit for a gas discharge lamp according to the present invention includes a transformer having a primary run winding, a primary start winding and a secondary winding. The primary run winding is coupled to a source of an AC run signal. The secondary winding is coupled to the gas discharge lamp. A current sensor is coupled in series with the gas discharge lamp to sense current flow through the lamp. A high frequency oscillator is coupled to the primary start winding for providing a high frequency start signal to the primary start winding. In a start phase, the oscillator provides the high frequency start signal to the primary start winding to initiate ionization of the gas discharge lamp. Once the gas has sufficiently ionized in the lamp, the control circuit switches from the start phase to a run phase by removing the high frequency start signal from the primary start winding and applying the AC run signal to the primary run winding.

Abstract: A voltage inverter is disclosed. A clock circuit provides timing signals to the electronics of the system. Electronics include a circuit for controlling the phase relationship between a pair of square waves, an overcurrent protection circuit, an auto-on circuit, a low voltage shutdown circuit, and output driver transistors for driving a primary transformer. A power transformer is connected to the primary transformer, and the output of the inverter is taken from the secondary transformer. Voltage and current magnitude indicative feedback signals are provided from the output of the inverter with the voltage signal being monitored by the phase varying circuit and the current feedback signal being monitored by the overcurrent protection circuit. Control of the off-time between alternating pulses during a cycle of the output is controlled by overlapping the square waves controlling the driver transistors for exitation of the primary transformer.