Abstract: A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes an operational amplifier that is configured in a sample hold operation. The single-ended input is first clamped by a switch (34) to clamp the DC level therein for a given pixel. A switch (38) then samples the reset level onto a sampling capacitor (46), and a switch (42) thereafter samples the video signal onto one plate of a capacitor (50). The lower plates of the capacitors (46) and (50) are then equalized and the other plates thereof connected to the positive and negative inputs of the operational amplifier (68). An offset is provided by a programmable DAC (26) to account for the dark current offset. The output scale is adjusted or mapped by limiting the output between a negative and a positive reference input. The sampling capacitors (46) and (50) can be varied to vary the gain of the amplifier.

Abstract: A pipelined data converter current biasing system employs a frequency-to-voltage converter (FVC) operational to convert a plurality of desired sampling frequencies to a plurality of output voltages and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents. The plurality of bias currents function to bias the data converter operational amplifiers such that the data converter power consumption is dependent on the plurality of sampling frequencies in a way that optimizes power consumed by the data converter with respect to the sampling frequency.

Abstract: A pipelined data converter current biasing system employs a frequency-to-voltage converter (FVC) operational to convert a plurality of desired sampling frequencies to a plurality of output voltages and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents. The plurality of bias currents function to bias the data converter operational amplifiers such that the data converter power consumption is dependent on the plurality of sampling frequencies in a way that optimizes power consumed by the data converter with respect to the sampling frequency.

Abstract: A pipelined analog-to-digital converter system (10) is responsive to an analog input signal (18). The system includes four pipeline stages (11-14), which each produce a respective digital output (26-29) that is coupled to a combining circuit (16). The combining circuit generates the digital output (41) of the system. Each pipeline stage includes an analog-to-digital converter (101), which generates the digital output for that stage. A shuffler circuit (103) randomly shuffles the bits of this digital output, in order to generate shuffled switching signals, which in turn are used to control electronic switches (206-209, 211-214) associated with several capacitors (C1-C4). By randomly shuffling the switching signals, the effects caused by variation of any capacitor from an ideal value are randomized. This avoids nonlinearity such as harmonic distortion in the analog output signal (21) from that stage.

Abstract: A pipelined analog-to-digital converter system (10) is responsive to an analog input signal (18). The system includes four pipeline stages (11-14), which each produce a respective digital output (26-29) that is coupled to a combining circuit (16). The combining circuit generates the digital output (41) of the system. Each pipeline stage includes an analog-to-digital converter (101), which generates the digital output for that stage. A shuffler circuit (103) randomly shuffles the bits of this digital output, in order to generate shuffled switching signals, which in turn are used to control electronic switches (206-209, 211-214) associated with several capacitors (C1-C4). By randomly shuffling the switching signals, the effects caused by variation of any capacitor from an ideal value are randomized. This avoids nonlinearity such as harmonic distortion in the analog output signal (21) from that stage.

Abstract: A differential switching circuit includes: a first inverter 46; a first pull-up transistor 43 coupled between the first inverter 46 and a high-side power supply node; a first pull-down transistor 34 coupled between the first inverter 46 and a low-side power supply node; an output node of the first inverter 46 coupled to a control node of the first pull-up transistor 43 and a control node of the first pull-down transistor 34; a second inverter 47; a second pull-up transistor 45 coupled between the second inverter 47 and the high-side power supply node; a second pull-down transistor 36 coupled between the second inverter 47 and the low-side power supply node; and an output node of the second inverter 47 coupled to a control node of the second pull-up transistor 45 and a control node of the second pull-down transistor 36, wherein the first and second inverters 46 and 47 are coupled together between the inverters and the pull-up transistors 43 and 45, and between the inverters and the pull-down transistors 34 and

Abstract: A skewless differential switching circuit uses skewless switching elements to convert complementary signals with skew into complementary output signals with minimal time skew between the output signals and with equalized rise and fall times of the output signals for minimum harmonic distortion.

Abstract: A trimming circuit for a gain stage in a pipeline analog-to-digital converter includes an amplification stage (30) having associated therewith on one input thereof a coupling capacitor (38). In parallel with the coupling capacitor is provided a trimming network. The trimming network includes a series configuration of a coupling capacitor and a plurality of trimming capacitors, which trimming capacitors can be disposed in parallel with each other. Each of the trimming capacitors has associated therewith a switch which allows them to be selectively disposed in series with a coupling capacitor (42) and in parallel with each other. This trimming network is connected in parallel with the sampling capacitor (38). The input to the amplifier is isolated from the trimming network with a buffer (62) which is operable to isolate the impedance of the trimming capacitors from the input and from preceding stages.

Abstract: A trimming algorithm for a pipeline A/D converter includes the step of trimming the input sampling capacitor on each of the gain stages for each stage of the pipeline A/D converter. The input thereof is swept from a minimum to a maximum analog voltage and then the integral non-linearity (INL) of the A/D converter determined. The maximum transitions are then examined to determine which transitions are associated with which stage. The transitions for a given stage then constitute the gain error for these stages. The trim values are determined from this gain error and then the trim values incorporated into each of the gain stages.

Abstract: An integrated circuit (IC) configurable as transmitter/receiver includes a method of preventing unauthorized learning and reproduction of an access code as a security measure. When the IC is configured as a receiver and placed in the learn mode, a flag is set in a memory of a microcontroller. If later configured as a transmitter, the microcontroller checks the flag upon power up and if the flag is set, the stored code is randomized so transmission of it is impossible.

Abstract: A pipelined analog-to-digital converter is disclosed having a plurality of sample and hold converter stages, each having an interstage amplifier (28) associated therewith. This is a differential amplifier that is implemented without common-mode feedback. The sample and hold stage operates on a reset phase and a gain/DAC phase, wherein the output of the reconstructive DAC is summed with the input to the amplifier (28). A differential input amplifier (60) has the inputs thereof set to common-mode input voltage with a feedback capacitor biased to a common-mode output bias point. During the gain/DAC phase, the bias input is removed and the feedback capacitor connected across the input/output of the amplifier (60). This effectively establishes the common-mode bias points for use by the amplifier (60) during the gain/DAC phase.

Abstract: A computer implemented method transmits and receives an information signal. A common start position is established for the receive mode where the information signal is received and a transmit mode where the information signal is transmitted. Either the receive mode to receive the information signal or the transmit mode to transmit the information signal is entered subsequent to establishing the common position. The start position is returned to after the receive mode the transmit the learn mode and the self-test mode has been entered.

Abstract: An integrated circuit configurable as a transmitter/receiver includes learn capabilities that allows a receiver IC to memorize the identification pattern of a specific transmitter.

Abstract: A System and method for calibrating a chip after packaging including providing a packaged chip, providing programmable non-volatile storage having a plurality of non-volatile storage elements in the chip and providing a volatile storage having a plurality of volatile storage elements in the chip with one volatile storage element associated with one non-volatile storage element. The chip includes circuitry responsive to a predetermined signal to permit the non-volatile storage to be programmed in accordance with data stored in the volatile storage and to a predetermined signal to prevent external alteration of the non-volatile storage. The non-volatile storage is preferably a plurality of fuses. The volatile storage is preferably a shift register.

Abstract: An integrated circuit (IC) configurable as transmitter/receiver includes a microcontroller to aid in decoding a pulse width modulated serial dam stream. The microcontroller accomplishes the decoding with the aid of a counter and an external clock signal without the necessity of using interrupts. Edge detection circuitry detects the rising and the rising edge of the incoming data pulse. The external clock signal clocks a counter to determine how many clock signals the incoming pulse corresponds to. The microcontroller polls the counter on the rising edge and the falling edge.

Abstract: A remote control access system uses a transmitter and a receiver. The transmitter generates an encrypted identification code which the receiver decrypts and grants access to the system if the decrypted code matches an identification code stored in the receiver. The encryption occurs by taking a 40 bit identification code and forming 5 bytes (8 bytes each). The 5 bytes are logic exclusive OR'd to form a 5 byte wide encrypted code. Decryption occurs by performing the opposite exclusive OR operation on the 5 byte wide encrypted code to convert it back to the 5 byte identification code. The 4 most significant bytes of the decrypted code are compared against the 4 most significant bytes of the previous stored decrypted code in the receiver. If the comparison yields a zero, this means the least significant byte will be within 2.sup.8 or 256 of each other and access will be granted.

Abstract: A transmitted data stream in a remote control system is a serial data stream having a synchronization sequence and a data sequence. The data sequence is encoded into a symbol comprised of a series of data bits wherein a 110 may represent a logic 1 and a 011 may represent a logic 0. A self adaptive filter adjusts its gain and offset to determine the duration of one bit. Providing a serial code format wherein the synchronization sequence has a smiller duty cycle as the duty cycle of a symbol aids the self adaptive filter to set its threshold switching level accurately and quickly, thus aiding the receiver to decode the transmitted data stream.

Abstract: An improved electrically erasable read only memory (EEPROM) includes a EEPROM cell and a static random access memory (SRAM) cell. Complementary pairs of complementary metal oxide semiconductor (CMOS) transistors connect the gates of transistors forming the EEPROM cell to either the corresponding data nodes of the SRAM cell or to a fixed read or nonzero test voltage. When formed into an array, it is not necessary to replicate differential sense circuitry in every cell. EEPROM transistor pairs are combined into columns which share a common sense latch. The nonsero test voltage allows for measurement of the actual threshold voltages (V.sub.T) of each EEPROM device individually.

Abstract: In a remote control system, a receiver demodulates an incoming signal that is typically RF into a digital signal. Signal shaping is required in order to transform small AC signal variations into clean, full-level digital signals. An increased sensitivity signal shaper circuit uses AC coupling with a fully differential architecture. A capacitor couples the input signal to a fully differential operational amplifier where a feedback capacitor sets the gain and a switched capacitor sets the time constant and operating point. The differential operational amplifier has a differential output that is fed into a single ended output comparator that is followed by a schmidt trigger which restores the signal to full logic levels.

Abstract: A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent to the Schottky barrier 40 and is separated from the conductive contact 36 by a portion of the semiconductor layer 24. No direct electrical path exists between the guard ring 26 and the conductive contact 36.