Patents by Inventor Eric G. Webb
Eric G. Webb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9447505Abstract: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer.Type: GrantFiled: June 4, 2015Date of Patent: September 20, 2016Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Eric G. Webb, David W. Porter
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Publication number: 20150267306Abstract: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer.Type: ApplicationFiled: June 4, 2015Publication date: September 24, 2015Inventors: Steven T. Mayer, Eric G. Webb, David W. Porter
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Publication number: 20140014522Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.Type: ApplicationFiled: July 23, 2013Publication date: January 16, 2014Applicant: Novellus Systems, Inc.Inventors: Steven T. Mayer, John Stephen Drewery, Eric G. Webb
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Patent number: 8500985Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.Type: GrantFiled: July 13, 2007Date of Patent: August 6, 2013Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, John Stephen Drewery, Eric G. Webb
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Patent number: 8470191Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.Type: GrantFiled: August 6, 2007Date of Patent: June 25, 2013Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
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Patent number: 8415261Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: October 11, 2011Date of Patent: April 9, 2013Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 8257781Abstract: A main reservoir holds cool reactant liquid. A reaction vessel for treating a substrate is connected to the main reservoir by a feed conduit. A heater is configured to heat reactant liquid in the feed conduit before the liquid enters the reaction vessel. Preferably, the heater is a microwave heater. A recycle conduit connects the reaction vessel with the main reservoir. Preferably, a recycle cooler cools reactant liquid in the recycle conduit before the liquid returns to the main reservoir. Preferably, an accumulation vessel is integrated in the feed conduit for accumulating, heating, conditioning and monitoring reactant liquid before it enters the reaction vessel. Preferably, a recycle accumulator vessel is integrated in the recycle conduit to accommodate reactant liquid as it empties out of the reaction vessel.Type: GrantFiled: August 11, 2005Date of Patent: September 4, 2012Assignee: Novellus Systems, Inc.Inventors: Eric G. Webb, Steven T. Mayer, David Mark Dinneen, Edmund B. Minshall, Christopher M. Bartlett, R. Marshall Stowell, Mark T. Winslow, Avishai Kepten, Jingbin Feng, Norman D. Kaplan, Richard K. Lyons, John B. Alexy
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Patent number: 8158532Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.Type: GrantFiled: November 20, 2006Date of Patent: April 17, 2012Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
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Patent number: 8043958Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: September 3, 2010Date of Patent: October 25, 2011Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 7947163Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.Type: GrantFiled: August 6, 2007Date of Patent: May 24, 2011Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, John Stephen Drewery, Eric G. Webb
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Patent number: 7897198Abstract: Electroless plating is performed to deposit conductive materials on work pieces such as partially fabricated integrated circuits. Components of an electroless plating bath are separately applied to a work piece by spin coating to produce a very thin conductive layer (in the range of a few hundred angstroms). The components are typically a reducing agent and a metal source.Type: GrantFiled: September 3, 2002Date of Patent: March 1, 2011Assignee: Novellus Systems, Inc.Inventors: Heung L. Park, Eric G. Webb, Jonathan D. Reid, Timothy Patrick Cleary
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Patent number: 7811925Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: July 31, 2008Date of Patent: October 12, 2010Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 7690324Abstract: During fluid treatment of a substrate surface, a carrier/wafer assembly containing a substrate wafer closes the top of a microcell container. The carrier/wafer assembly and the container walls define a thin enclosed treatment volume that is filled with treating fluid, such as electroless plating solution. The thin fluid-treatment volume typically has a volume in a range of about from 100 ml to 500 ml. Preferably a container is heated and the treating fluid is pre-heated before being injected into the container. Preferably, the chemical composition, temperature, and other properties of fluid in the thin enclosed fluid-treatment volume are dynamically variable. A rinse shield and a rinse nozzle are located above the container. A carrier/wafer assembly in a rinse position substantially closes the top of the rinse shield.Type: GrantFiled: August 9, 2005Date of Patent: April 6, 2010Assignee: Novellus Systems, Inc.Inventors: Jingbin Feng, Steven T. Mayer, Daniel Mark Dinneen, Edmund B. Minshall, Christopher M. Bartlett, Eric G. Webb, R. Marshall Stowell, Mark T. Winslow, Avishai Kepten, Norman D. Kaplan, Richard K. Lyons, John B. Alexy
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Publication number: 20090280243Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.Type: ApplicationFiled: July 13, 2007Publication date: November 12, 2009Applicant: Novellus Systems, Inc.Inventors: Steven T. Mayer, John Stephen Drewery, Eric G. Webb
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Publication number: 20090277867Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.Type: ApplicationFiled: November 20, 2006Publication date: November 12, 2009Applicant: Novellus Systems, Inc.Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
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Publication number: 20090280649Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.Type: ApplicationFiled: August 6, 2007Publication date: November 12, 2009Applicant: Novellus Systems, Inc.Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
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Publication number: 20090277801Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.Type: ApplicationFiled: August 6, 2007Publication date: November 12, 2009Applicant: Novellus Systems, Inc.Inventors: Steven T. Mayer, John Stephen Drewery, Eric G. Webb
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Patent number: 7605082Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: October 13, 2005Date of Patent: October 20, 2009Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 7442267Abstract: A ruthenium-containing thin film is formed. Typically, the ruthenium-containing thin film has a thickness in a range of about from 1 nm to 20 nm. The ruthenium-containing thin film is annealed in an oxygen-free atmosphere, for example, in N2 forming gas, at a temperature in a range of about from 100° C. to 500° C. for a total time duration of about from 10 seconds to 1000 seconds. Thereafter, copper or other metal is deposited by electroplating or electroless plating onto the annealed ruthenium-containing thin film. In some embodiments, the ruthenium-containing thin film is also treated by UV radiation.Type: GrantFiled: November 29, 2004Date of Patent: October 28, 2008Assignee: Novellus Systems, Inc.Inventors: Eric G. Webb, Jonathan D. Reid, Seyang Park, Johanes H. Sukamto
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Patent number: 7341946Abstract: Methods are provided for electrochemically depositing copper on a work piece. One method includes the step of depositing overlying the work piece a barrier layer having a surface and subjecting the barrier layer surface to a surface treatment adapted to facilitate deposition of copper on the barrier layer. Copper then is electrochemically deposited overlying the barrier layer.Type: GrantFiled: November 10, 2003Date of Patent: March 11, 2008Assignee: Novellus Systems, Inc.Inventors: Sridhar K. Kailasam, John Drewery, Jonathan D. Reid, Eric G. Webb, Johanes H. Sukamto