Patents by Inventor Eric Gerritsen
Eric Gerritsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10693026Abstract: The invention concerns a method for producing a photovoltaic module, comprising:?—providing a plurality of bifacial photovoltaic cells each having a short-circuit current ratio (B),?—asymmetrically cutting each cell into two portions, such that the ratio between the surface areas of said portions is substantially equal to the short-circuit current ratio (B) of said cell or to the average short-circuit ratio of the set of cells,?—juxtapositioning said cell portions in a main plane of the module in order to form pairs of cell portions chosen such that the front face of the first portion has a short-circuit current substantially equal to the short-circuit current of the rear face of the second portion, said portions being arranged such that the front face of the first portion and the rear face of the second portion coincide with the front face of the module,?—creating an electrical connection of the front face of the first portion with the rear face of the second portion.Type: GrantFiled: July 27, 2015Date of Patent: June 23, 2020Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Paul Lefillastre, Eric Gerritsen
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Publication number: 20170236963Abstract: The invention concerns a method for producing a photovoltaic module, comprising:•—providing a plurality of bifacial photovoltaic cells each having a short-circuit current ratio (B),•—asymmetrically cutting each cell into two portions, such that the ratio between the surface areas of said portions is substantially equal to the short-circuit current ratio (B) of said cell or to the average short-circuit ratio of the set of cells,•—juxtapositioning said cell portions in a main plane of the module in order to form pairs of cell portions chosen such that the front face of the first portion has a short-circuit current substantially equal to the short-circuit current of the rear face of the second portion, said portions being arranged such that the front face of the first portion and the rear face of the second portion coincide with the front face of the module,•—creating an electrical connection of the front face of the first portion with the rear face of the second portion.Type: ApplicationFiled: July 27, 2015Publication date: August 17, 2017Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Paul Lefillastre, Eric Gerritsen
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Publication number: 20160301359Abstract: The invention relates to a photovoltaic structure comprising a first wall and a second wall defining an inner space therebetween, the first wall being at least partially transparent to solar radiation, the second wall comprising an inner surface that is at least partially reflective with respect to solar radiation across from the inner surface of the first wall, the first wall being part of a closed enclosure and the second wall being arranged inside said enclosure, and photovoltaic modules each comprising a plurality of bifacial photovoltaic cells, arranged on the outer surface of the first wall, such that when the structure is exposed to solar radiation, a first portion of the incident radiation is transmitted to the outer surface of said bifacial photo voltaic cells, and a second portion of said incident radiation is transmitted through a portion of the first wall and reflects at least partially on the inner surface of the second wall, said reflected portion being transmitted through the first wall to theType: ApplicationFiled: December 17, 2014Publication date: October 13, 2016Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Eric Gerritsen, Christophe Mangeant
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Patent number: 9379020Abstract: A method of selective formation of silicide on a semiconductor wafer, wherein the metal layer is deposited over the entire wafer prior to application of the SiProt mask such that any etching of the mask does not cause any surface deterioration of the silicon wafer.Type: GrantFiled: September 26, 2007Date of Patent: June 28, 2016Assignee: NXP B.V.Inventors: Eric Gerritsen, Veronique De-Jonghe, Srdjan Kordic
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Patent number: 9012765Abstract: The invention relates to a reflective device for a photovoltaic module formed by a plurality of bifacial photovoltaic cells or rows of said cells spaced apart from one another, each cell having an active front face and an active rear face that can capture photons from incident light rays falling on the front and rear faces. The device comprises at least one reflective module to be placed under the cells substantially in line with the gap(s) separating two adjacent cells or two rows of adjacent cells. The reflective module comprises: a first portion, of which the surfaces that are oriented towards the gap have a first curvature such as to send all or part of the incident photons towards the rear face of the cells; and a second portion mounted on the first portion, of which the surfaces oriented towards the gap have a second curvature such as to send all or part of the incident photons towards the rear face of the cells, the second curvature being different from the first curvature.Type: GrantFiled: December 10, 2010Date of Patent: April 21, 2015Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Vincenzo Sanzone, Eric Gerritsen, Philippe Thony
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Publication number: 20130112241Abstract: The invention relates to a photovoltaic module comprising a plurality of photovoltaic cells electrically connected in series via connection means comprising electrical conductors. Each connection means comprises an optical device having a reflection-diffractive or transmission-diffractive optical behaviour, and each connection means consists of a sheet formed from a material transparent to incident rays containing at least one network of electrical conductor wires.Type: ApplicationFiled: October 28, 2010Publication date: May 9, 2013Applicant: Commissariat A L'Energie Atomique Et Aux Energies AlternativesInventors: Eric Gerritsen, Philippe Thony
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Publication number: 20120247533Abstract: The invention relates to a reflective device for a photovoltaic module formed by a plurality of bifacial photovoltaic cells or rows of said cells spaced apart from one another, each cell having an active front face and an active rear face that can capture photons from incident light rays falling on the front and rear faces. The device comprises at least one reflective module to be placed under the cells substantially in line with the gap(s) separating two adjacent cells or two rows of adjacent cells. The reflective module comprises: a first portion, of which the surfaces that are oriented towards the gap have a first curvature such as to send all or part of the incident photons towards the rear face of the cells; and a second portion mounted on the first portion, of which the surfaces oriented towards the gap have a second curvature such as to send all or part of the incident photons towards the rear face of the cells, the second curvature being different from the first curvature.Type: ApplicationFiled: December 10, 2010Publication date: October 4, 2012Applicant: Commissariat A L'Energie Atomique Et Aux Energies AlternativesInventors: Vincenzo Sanzone, Eric Gerritsen, Philippe Thony
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Publication number: 20100013090Abstract: A method of selective formation of suicide on a semiconductor wafer, wherein the metal layer (12) is deposited over the entire wafer prior to application of the SiProt mask (10, 16, 22) such that any etching of the mask (10, 16, 22) does not cause any surface deterioration of the silicon wafer.Type: ApplicationFiled: September 26, 2007Publication date: January 21, 2010Applicant: NXP, B.V.Inventors: Eric Gerritsen, Veronique De-Jonghe, Srdjan Kordic
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Patent number: 6939812Abstract: There is a method of manufacturing a semiconductor device. In an example embodiment, the method comprises applying a semiconductor substrate that is provided with a conductor at a surface. The conductor has a top surface portion and sidewall portions, of which at least the top surface portion is provided with an etch stop layer comprising silicon carbide. A dielectric layer is applied. A via is etched in the dielectric layer over the conductor and, and stopping on the etch stop layer to create an exposed part of the etch stop layer. Inside the via from at least the top surface portion of the conductor, the exposed part of the etch stop layer is removed. The via is filled with a conductive material.Type: GrantFiled: March 12, 2001Date of Patent: September 6, 2005Assignee: Koninklijke Philips Electronics N.V.Inventors: Marcel Eduard Irene Broekaart, Josephus Franciscus Antonius Maria Guelen, Eric Gerritsen
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Patent number: 6812121Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.Type: GrantFiled: May 16, 2001Date of Patent: November 2, 2004Assignees: STMicroelectronics S.A., Koninklijke Philips Electronics N.V.Inventors: Eric Gerritsen, Bruno Baylac, Marie-Thérèse Basso
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Patent number: 6677234Abstract: In a crystalline silicon body a shallow trench insulation is made by etching a groove and filling it with silicon oxide. Ridges of polysilicon are made on the surface of the silicon body by applying a layer of polysilicon and patterning it with a known technique. Spacers of silicon nitride are provided on the side walls of the polysilicon ridges. A first layer of silicon nitride, a second layer of TEOS and a patterned resist layer are applied. The TEOS layer is etched by immersion in a solution of 0.36% HF for 14 minutes. Subsequently, the resist is stripped in H2SO4 or peroxide. The silicon nitride layer is etched by immersion in phosphoric acid of 165° C. for 15 minutes using the TEOS layer as a mask. A titanium layer is applied. Subsequently, the body is rapidly heated to a temperature of 760° C. at which it is kept for 20 seconds. During this rapid thermal treatment titanium silicide is formed at locations where the titanium is in contact with silicon i.e.Type: GrantFiled: August 6, 1999Date of Patent: January 13, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Josephus F. A. M. Guelen, Eric Gerritsen, Walter J. A. De Coster
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Publication number: 20030207569Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.Type: ApplicationFiled: May 16, 2001Publication date: November 6, 2003Applicant: STMicroelectronics S.A. and Koninklijke Philips Electronics N.V.Inventors: Eric Gerritsen, Bruno Baylac, Marie-Therese Basso
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Publication number: 20010046784Abstract: A method of manufacturing an electronic device, a semiconductor device in particular but not exclusively, which method comprises the steps of:Type: ApplicationFiled: March 12, 2001Publication date: November 29, 2001Inventors: Marcel Eduard Irene Broekaart, Josephus Franciscus Antonius Maria Guelen, Eric Gerritsen
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Patent number: 6281556Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.Type: GrantFiled: March 12, 1999Date of Patent: August 28, 2001Assignees: STMicroelectronics S.A., Koninklijke Philips Electronics N.V.Inventors: Eric Gerritsen, Bruno Baylac, Marie-Thérèse Basso