Patents by Inventor Eric Godas

Eric Godas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240185926
    Abstract: A variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. A touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. Techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. Variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.
    Type: Application
    Filed: November 22, 2023
    Publication date: June 6, 2024
    Inventors: Huai-Yuan Tseng, Kishore Kumar Mucherla, William Charles Filipiak, Eric N. Lee, Andrew Bicksler, Ugo Russo, Niccolo' Righetti, Christian Caillat, Akira Goda, Ting Luo, Antonino Pollio
  • Patent number: 11960722
    Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tomoharu Tanaka, Huai-Yuan Tseng, Dung V. Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda, James Fitzpatrick, Dave Ebsen
  • Patent number: 11935853
    Abstract: An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 19, 2024
    Inventors: Eric N. Lee, Akira Goda
  • Publication number: 20240087651
    Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Dung V. Nguyen, Giovanni Maria Paolucci, James Fitzpatrick, Eric N. Lee, Dave Scott Ebsen, Tomoharu Tanaka
  • Patent number: 11922993
    Abstract: A device includes an array of memory cells with a first word line coupled to at least a subset of the array of memory cells and control logic coupled to the first word line. The control logic to detect, within a queue, a first read command to read first data from a first page of the subset and a second read command to read second data from a second page of the subset. The control logic is further to cause a voltage applied to the first word line to move to a target value. The control logic is further to cause a page buffer to sense the first data from a first bit line coupled to the first page and to sense the second data from a second bit line coupled to the second page. The control logic is further to cause the first word line to be discharged.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Koichi Kawai, Sundararajan Sankaranarayanan, Eric Nien-Heng Lee, Akira Goda
  • Patent number: 9794285
    Abstract: A system, method, and computer program product are provided for detecting hacked modems in a cable network system. A cable Internet service provider can provide the disclosed heuristic to determine whether a particular cable modem has likely been hacked by obtaining a score corresponding to this likelihood. This score, as well as information regarding failure and success of various tests, can be used to generate a report identifying the likelihood that various modems have been hacked.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 17, 2017
    Assignee: CSC Holdings, LLC
    Inventors: Eric Godas, John Pomeroy, Brian Daniels
  • Publication number: 20060077951
    Abstract: A method of redirecting network traffic is described, in which traffic originating from a first network element is modified by rewriting the Type of Service field of an Internet Protocol packet, and the modified traffic is redirected to a second network element.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 13, 2006
    Inventor: Eric Godas