Patents by Inventor Eric Gouldey
Eric Gouldey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11681611Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.Type: GrantFiled: December 11, 2020Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
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Publication number: 20210240609Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.Type: ApplicationFiled: December 11, 2020Publication date: August 5, 2021Inventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
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Patent number: 10866888Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.Type: GrantFiled: January 11, 2018Date of Patent: December 15, 2020Assignee: Intel CorporationInventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
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Publication number: 20190213120Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Omid Azizi, Amin Firoozshahian, Andreas Kleen, Mahesh Madhav, Mahesh Maddury, Chandan Egbert, Eric Gouldey
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Patent number: 10248574Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.Type: GrantFiled: May 30, 2017Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Rupin H. Vakharwala, Eric A. Gouldey, Camron B. Rust, Brett Ireland, Rajesh M. Sankaran
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Publication number: 20180349288Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.Type: ApplicationFiled: May 30, 2017Publication date: December 6, 2018Inventors: Rupin H. Vakharwala, Eric A. Gouldey, Camron B. Rust, Brett Ireland, Rajesh M. Sankaran
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Patent number: 9170946Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.Type: GrantFiled: December 21, 2012Date of Patent: October 27, 2015Assignee: Intel CorporationInventors: Herbert H. Hum, James R. Vash, Eric A. Gouldey, Ganesh Kumar, David Bubien, Manoj K. Arora, Luke Chang, Lavanya Nama, Mahak Gupta
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Patent number: 9063855Abstract: A method for detecting errors in a processing device is disclosed. A data source unit of a processing device transmits data and a qualifier synchronously with the data, the qualifier to indicate the data is uncorrectable. At least one intermediate functional unit in the processing device receives the data and the qualifier. The at least one intermediate functional unit detects the data is uncorrectable based on the qualifier. The at least one intermediate functional unit transmits, without using, the data and the qualifier synchronously with the data to a data consumer unit of the processing device. The data consumer unit receives the data and the qualifier. The data consumer unit detects the data is uncorrectable based on the qualifier. The data consumer unit maintains, without using the data and the qualifier.Type: GrantFiled: March 14, 2013Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Cameron B. McNairy, Anil Agrawal, Jenna S. Mayfield, Eric A. Gouldey, Mark Millican
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Publication number: 20140281747Abstract: A method for detecting errors in a processing device is disclosed. A data source unit of a processing device transmits data and a qualifier synchronously with the data, the qualifier to indicate the data is uncorrectable. At least one intermediate functional unit in the processing device receives the data and the qualifier. The at least one intermediate functional unit detects the data is uncorrectable based on the qualifier. The at least one intermediate functional unit transmits, without using, the data and the qualifier synchronously with the data to a data consumer unit of the processing device. The data consumer unit receives the data and the qualifier. The data consumer unit detects the data is uncorrectable based on the qualifier. The data consumer unit maintains, without using the data and the qualifier.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Cameron B. McNairy, Anil Agrawal, Jenna S. Mayfield, Eric A. Gouldey, Mark Millican
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Publication number: 20140181394Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Inventors: Herbert H. Hum, James R. Vash, Eric A. Gouldey, Ganesh Kumar, David Bubien, Manoj K. Arora, Luke Chang, Lavanya Nama, Mahak Gupta