Abstract: Computing device (100) comprising a main memory (104) configured to store a sparse matrix in a dense vector format (106, 108, 110) and to store a second vector (112) or a second matrix, a computing unit (102) configured to multiply the sparse matrix by the second vector or by the second matrix, and a streamer (114) comprising: an indexed loading block (116) comprising a secondary memory (118) and a FIFO memory (120) for requests to send values stored in the secondary memory to the computing unit; an indexed loading engine (122) configured to sequentially generate and store requests in the FIFO request memory according to an order in which the values are intended to be sent to the computing unit; the request storage order being calculated and stored in the form of firmware (124).

Abstract: The present description concerns an electronic circuit (10) for providing a digital signal (Sn) comprising a succession of ramps, the electronic circuit being clocked by a clock signal, the electronic circuit being configured to supply a number Nout of digital values of the digital signal at each cycle of the clock signal, Nout being greater than 1. The electronic circuit comprises a first memory (30) in which are stored, for each ramp, first data, and a second memory (32) in which are stored second data relative to the numbers of cycles of the clock signal over which some of the ramps extend, and a first circuit (40) configured to read from the first memory the first data relative to a plurality of successive ramps and from the second memory the second data associated with said plurality of successive ramps, and to supply said digital values.

Abstract: The present description concerns an electronic circuit (10) for providing a digital signal (Sn) comprising a succession of ramps, the electronic circuit being clocked by a clock signal, the electronic circuit being configured to supply a number Nout of digital values of the digital signal at each cycle of the clock signal, Nout being greater than 1. The electronic circuit comprises a first memory (30) in which are stored, for each ramp, first data, and a second memory (32) in which are stored second data relative to the numbers of cycles of the clock signal over which some of the ramps extend, and a first circuit (40) configured to read from the first memory the first data relative to a plurality of successive ramps and from the second memory the second data associated with said plurality of successive ramps, and to supply said digital values.

Abstract: A multi-core architecture including: a plurality of processing devices, each processing device including a single processor or a cluster of processors; and a lock manager associated with each processing device, each lock manager being configured to: store a first data value indicating of whether or not it currently owns a first lock, the first lock authorizing access to a resource; and permit an owner of the first lock to be determined by one or more lock managers by broadcasting, over an interconnection network to each of the other lock managers, at least one message.

Abstract: A cache coherence management system includes: a set of directories distributed between nodes of a network for interconnecting processors including cache memories, each directory including a correspondence table between cache lines and information fields on the cache lines; and a mechanism updating the directories by adding, modifying, or deleting cache lines in the correspondence tables. In each correspondence table and for each cache line identified, at least one field is provided for indicating a possible blocking of a transaction relative to the cache line considered, when the blocking occurs in the node associated with the correspondence table considered. The system further includes a mechanism detecting fields indicating a transaction blocking and restarting each transaction detected as blocked from the node in which it is indicated as blocked.

Abstract: A multi-core architecture including: a plurality of processing devices, each processing device including a single processor or a cluster of processors; and a lock manager associated with each processing device, each lock manager being configured to: store a first data value indicating of whether or not it currently owns a first lock, the first lock authorizing access to a resource; and permit an owner of the first lock to be determined by one or more lock managers by broadcasting, over an interconnection network to each of the other lock managers, at least one message.

Abstract: This method for executing a request to exchange data, between first and second disjoint physical addressing spaces controlled by first and second distinct circuits for first and second respective software processes, comprises the creation of a communication channel between these two circuits. It further comprises sending, by the first process, of said request to exchange data, this request designates a virtual address in a virtual addressing space of the second process, and execution of the request to exchange data between the disjoint physical addressing spaces of the two processes, without invoking a processor executing the second process. During creation of the channel, a translation of the virtual addressing space of the second process into its physical addressing space is created and associated with this channel in the second circuit. During execution of the request, data for identification of the channel is added to the virtual address designated in the request.

Abstract: A system for data processing with management of a cache consistency in a network of processors including cache memories, the network including plural nodes for access to a main memory interconnected with one another, a set of directories being distributed between nodes of the network, each directory including a table of correspondence between cache lines and information fields on the cache lines. The system includes a first sub-network for interconnection of the nodes with one another, implementing a first message transmission protocol providing read/write access to the directories during any passage in the corresponding nodes of a message passing through the first sub-network, and a second sub-network for interconnection of the nodes with one another, implementing a second message transmission protocol, the second protocol excluding any read/write access to the directories during any passage in the corresponding nodes of a message passing through the second sub-network.

Abstract: A system for managing correspondence between a cache memory, subdivided into a plurality of cache areas, and a main memory, subdivided into a plurality of memory areas, includes: a mechanism allocating, to each area of the main memory, at least one area of the cache memory; a mechanism temporarily assigning, to any data row stored in one of the areas of the main memory, a cache row included only in one cache area allocated to the main memory area wherein the data row is stored; and a mechanism generating and updating settings of the allocation by activating the allocation mechanism, the temporary assigning mechanism configured to determine a cache row to be assigned to a data row based on the allocation settings.

Abstract: A system for data processing with management of a cache consistency in a network of processors including cache memories, the network including plural nodes for access to a main memory interconnected with one another, a set of directories being distributed between nodes of the network, each directory including a table of correspondence between cache lines and information fields on the cache lines. The system includes a first sub-network for interconnection of the nodes with one another, implementing a first message transmission protocol providing read/write access to the directories during any passage in the corresponding nodes of a message passing through the first sub-network, and a second sub-network for interconnection of the nodes with one another, implementing a second message transmission protocol, the second protocol excluding any read/write access to the directories during any passage in the corresponding nodes of a message passing through the second sub-network.

Abstract: A cache coherence management system includes: a set of directories distributed between nodes of a network for interconnecting processors including cache memories, each directory including a correspondence table between cache lines and information fields on the cache lines; and a mechanism updating the directories by adding, modifying, or deleting cache lines in the correspondence tables. In each correspondence table and for each cache line identified, at least one field is provided for indicating a possible blocking of a transaction relative to the cache line considered, when the blocking occurs in the node associated with the correspondence table considered. The system further includes a mechanism detecting fields indicating a transaction blocking and restarting each transaction detected as blocked from the node in which it is indicated as blocked.

Abstract: A system for managing correspondence between a cache memory, subdivided into a plurality of cache areas, and a main memory, subdivided into a plurality of memory areas, includes: a mechanism allocating, to each area of the main memory, at least one area of the cache memory; a mechanism temporarily assigning, to any data row stored in one of the areas of the main memory, a cache row included only in one cache area allocated to the main memory area wherein the data row is stored; and a mechanism generating and updating settings of the allocation by activating the allocation mechanism, the temporary assigning mechanism configured to determine a cache row to be assigned to a data row based on the allocation settings.