Abstract: A computer implemented process compares signals communicated between a known position and a plurality of base stations in a cellular telephone system to determine the level of interference with a signal on a channel expected to serve the known position, and determines a value indicating a probability of interference with a signal on a channel expected to serve the known position.

Abstract: A method for detecting inequality in path balance in a cellular telephone system including the steps of providing data describing measured signal strength of signals received at a mobile unit and at a cell site in the absence of interference at a plurality of points describing the entire system; providing data describing measured signal strength of signals transmitted from each cell and from the mobile unit in the cellular telephone system; accumulating and averaging the data describing measured signal strength of signals received at the mobile unit and at the cell site to eliminate path loss variances between points and the cell site; selecting data describing measured signal strength of signals received at a mobile unit with path loss variances eliminated, data describing measured signal strength of signals transmitted from the mobile unit, data describing measured signal strength of signals received at a cell with path loss variances eliminated, data describing signal strength of signals transmitted from e

Abstract: A computer implemented process which includes furnishing data indicating the actual strengths of all signals to be transmitted by a plurality of cells each positioned at an individual physical position in a mobile communications system and to be received by a mobile unit at a plurality of points of an entire mobile communications system, relating data indicating the actual strengths of all signals to the physical positions from which the signals are to be transmitted, identifying cells transmitting signals likely to serve each point of the plurality of points, and comparing planned frequencies to be used at any position serving a point with planned frequencies to be used at other positions to identify cells transmitting signals which might interfere with signals transmitted by cells serving a point.

Abstract: A processor for a SPARC based RISC computer including a central processing unit including a register file having a pair of read ports and a write port, an instruction register for holding an instruction including addresses of registers to be read and written to, a multiplexor, and apparatus for controlling the multiplexor to transfer the address from a write position of the instruction register to the register file such that the information stored in the addressed register is transferred out of the register file through one of the read ports on the clock cycle following a store instruction.

Abstract: A primary, a secondary, and a tertiary cache, and a floating point pipeline having optimized complimentary characteristics are provided to a computer system for executing floating point instructions. The primary cache is direct mapped and having n.sub.1 cache lines, each having a cache line size of m.sub.1 floating point data word(s) and an access time of t.sub.1 clock cycle(s), where m.sub.1 and t.sub.1 are both small integer greater than or equal to 1. The secondary cache is fully associative having n.sub.2 cache lines, each having a cache line size of m.sub.2 floating point data words and an access time of t.sub.2 clock cycles, where n.sub.2 is a small integer, m.sub.2 is greater than m.sub.1, and t.sub.2 is a small integer greater than t.sub.1. The tertiary cache has n.sub.3 cache lines, each having a cache line size of m.sub.3 floating point data words and an access time of t.sub.3 clock cycles, where m.sub.3 is greater than m.sub.2 and t.sub.3 is a small integer greater than t.sub.2.

Abstract: A method and apparatus for loading a data value for a future LOAD instruction in a microprocessor by predicting the LOAD instruction's effective address. At each occurrence of a LOAD instruction, the effective address used is stored in a memory array which stores a last effective address and a next-to-last effective address. At a specified period before each LOAD instruction, the microprocessor loads a data value from a predicted effective memory address computed from the memory array. The predicted effective memory address is equal to the last effective address plus the difference between the last effective address and the next-to-last effective address. If the predicted effective address equals the actual effective address of the future LOAD instruction, the loaded data value is used.

Abstract: A processor having a plurality of windowed registers comprising IN, OUT and local window registers, where the IN registers of each window are addressable as the OUT registers of a logically-adjacent succeeding window. The processor also having a cache of two sets of IN/OUT registers with switchable addresses and a set of local cache registers. The addresses of the first set of IN/OUT registers can be changed to the addresses of the second set of IN/OUT registers, and vice versa, when the current window changes during a save or restore operation.

Abstract: A processor which has a plurality of windowed registers. Each of the windowed registers comprise IN, OUT and LOCAL window registers. The IN registers of each window are addressable as the OUT registers of a logically-adjacent succeeding window. The processor also has a cache of at least four sets of cache registers with switchable addresses. Each set of cache registers is capable of holding data of the IN, OUT or LOCAL window registers. The addresses of each set of cache registers are changed to the addresses of a different set of cache registers when the current window changes during a save or restore operation.

Abstract: A caching memory system including a translation look-aside buffer having a preselected number of lines of memory, each of said lines including storage for a virtual address and a physical address, apparatus for selectively varying the size of pages the virtual and physical addresses of which may be stored in the translation look-aside buffer, and apparatus for interrogating the virtual addresses to determine whether a requested address is stored in the translation look-aside buffer.

Abstract: A pipelined register cache for increasing a computer processor's execution speed by reducing the time required to access register data. A register cache is implemented to keep often-used registers in high-speed storage immediately available to the processor's arithmetic and logic unit (ALU). The register cache is constructed using a number of individual register stages which are connected in series such that the register information contained in each register stage is passed from one register stage to the next in a First-In, First-Out (FIFO) queue arrangement. Each register stage stores a register address tag for identifying the particular primary register being represented in that register stage, and a data value representing the actual register contents. When a register that is not represented in the cache is needed for a calculation, the register information is first loaded from the primary register storage into the first register stage of the register cache.

Abstract: A circuit for multiplying two binary numbers including apparatus for sorting one of the binary numbers into groups of variable lengths, each group including all contiguous ones beginning at the lowest order bit and all continguous zeroes beginning with the highest order one of the group; apparatus for selecting for each group starting with the lowest order group of bits a binary number equal to the value of the other one of the binary numbers multiplied by a selected binary number consisting of ones; apparatus for shifting the selected number right a number of bits equal to the number of zeros in the group; apparatus for adding a next binary number equal to the value of the other one of the binary numbers multiplied by a selected binary number consisting of ones equal to the number of ones in an individual group to the partial product for each remaining group; apparatus for shifting the partial result of the addition right a number of bits equal to the number of zeroes in the each group after the addition of

Abstract: A caching system which includes a main memory divided into a predetermined number of pages having a predetermined number of columns and lines of storage elements, a cache memory haivng the same number of lines of storage elements as the pages of main memory and a number of columns sufficient to store the information in any line of main memory plus the address of the information in main memory, apparatus for transferring between cache memory and main memory information and addresses indicative of the position in main memory represented by any particular information in cache memory, the addresses including an offset indicating the particular line of the page of main memory and a number of bits indicating only one of a limited number of pages which may be stored in the cache at one time, and a page number cache having a line number equal to the number of pages which may be stored in the cache and a column number sufficient to store the tag address of a line stored in the cache.