Abstract: This disclosure provides systems, methods and apparatus for processing, transmitting and displaying data received from an analyte sensor, such as a glucose sensor. The system may include a display device with at least one input device. In response to movement of or along the input device, the display device may change a glucose data output parameter and update an output of the display device using the changed output parameter.

Abstract: The digital amplification methods and kits provide the ability to estimate the fetal fraction of cell-free DNA (cfDNA) in a maternal sample, e.g., plasma or serum, by analysis of target sites that are differentially methylated in fetal and maternal cfDNA.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: An apparatus, system and method for protecting the confidentiality and integrity of a secure object running on a computer system by protecting the memory pages owned by the secure object, including assigning a secure object an ID, labeling the memory pages owned by a secure object with the ID of the secure object, maintaining an Access Control Monitor (ACM) table for the memory pages on the system, controlling access to memory pages by monitoring load and store instructions and comparing information in the ACM table with the ID of the software that is executing these instructions; and limiting access to a memory page to the owner of the memory page.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: According to examples, an apparatus includes a processor and a memory on which is stored machine readable instructions. The instructions may cause the processor to acquire technical characteristics of a client workload, access client policies, determine an infrastructure to implement the client workload based upon the acquired technical characteristics of the client workload, determine, based upon the determined server sizing and the accessed client policies, a recommended hosting provider that is to host the client workload, and output the determined server sizing and the recommended hosting provider.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: A sulphur denitrification system includes a liquid input fluidly coupled to a source of saltwater that includes nitrate; a liquid output fluidly coupled to the source of saltwater; a plurality of vertically-oriented tanks, at least one of the tanks including a liquid inlet that is fluidly coupled to the liquid input to receive a flow of the saltwater, a volume configured to enclose a plurality of sulphur particles that support denitrification bacteria that biologically transform the nitrate into at least one of nitrous oxide or nitrogen gas, and a liquid outlet fluidly coupled to the liquid output and the liquid inlets of the tanks; and a circulation system configured to circulate a portion of the saltwater though the liquid input to the liquid inlets of the plurality of tanks, through the plurality of tanks, and from the liquid outlets of the tanks to the liquid output and the liquid inlets of the tanks.

Abstract: A sulphur denitrification system includes a liquid input fluidly coupled to a source of saltwater that includes nitrate; a liquid output fluidly coupled to the source of saltwater; a plurality of vertically-oriented tanks, at least one of the tanks including a liquid inlet that is fluidly coupled to the liquid input to receive a flow of the saltwater, a volume configured to enclose a plurality of sulphur particles that support denitrification bacteria that biologically transform the nitrate into at least one of nitrous oxide or nitrogen gas, and a liquid outlet fluidly coupled to the liquid output and the liquid inlets of the tanks; and a circulation system configured to circulate a portion of the saltwater though the liquid input to the liquid inlets of the plurality of tanks, through the plurality of tanks, and from the liquid outlets of the tanks to the liquid output and the liquid inlets of the tanks.

Abstract: Provided herein include a degradation-promoted polymer and a method for making the degradation-promoted polymer. The degradation-promoted polymer has a composition containing one or more polymers and a degradation-promoting agent that includes Lactide and an organic acid. The organic acid may include at least one of succinic acid, levulinic acid, and lauric acid. The degradation-promoting agent can promote and control the degradation of the polymer in aqueous-based environments having different temperatures, pressures depths, and aqueous solutions. The method includes mixing a polymer with a degradation-promoting agent to produce a degradation-promoted polymer. Application for such degradation-promoted polymer can include but not limited to such as for example a process for opening new oil well, oil well work-over, or oil well cleanout, in which each well may have a different temperature and may require a different degradation rate of the polymer.

Abstract: An apparatus, system and method for protecting the confidentiality and integrity of a secure object running on a computer system by protecting the memory pages owned by the secure object, including assigning a secure object an ID, labeling the memory pages owned by a secure object with the ID of the secure object, maintaining an Access Control Monitor (ACM) table for the memory pages on the system, controlling access to memory pages by monitoring load and store instructions and comparing information in the ACM table with the ID of the software that is executing these instructions; and limiting access to a memory page to the owner of the memory page.

Abstract: The example systems, methods, and devices disclosed herein generally relate to generating create a supervised failure model for assets in the given fleet that is configured to receive operating data as inputs and output a prediction as to the occurrence of a given failure type at the asset. In some instances, a data analytics platform may create and use an unsupervised failure model for a subset of the assets, use the respective unsupervised failure models to detect a set of anomalies that are each suggestive of a prior failure occurrence, from the set of anomalies, identify a subset of anomalies that are each suggest of a prior failure occurrence of the given failure type, and create the supervised failure model using failure data for the identified subset of anomalies.