Patents by Inventor Eric Hao
Eric Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103895Abstract: Systems and methods for monitoring health of virtual machines (VMs) include determining a leader virtual machine (VM) count for a group of VM nodes hosted on a plurality of computing devices; selecting a number of the VM nodes of the group to serve as leader VMs for the group, the number of the VM nodes selected corresponding to the leader VM count; and periodically performing a peer VM monitoring process. The peer VM monitoring process includes periodically storing health information for each of the VM nodes of the group in a data store; periodically accessing the health information of each of the VM nodes to identify sick VMs using each of the leader VMs, respectively; and automatically performing a healing process on the sick VMs to improve a performance of the sick VMs.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Akshay Navneetlal MUTHA, Eric Phillip RODRIGUEZ, Peilin HAO
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Patent number: 8549266Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: GrantFiled: June 7, 2011Date of Patent: October 1, 2013Inventors: John P. Banning, Eric Hao, Brett Coon
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Publication number: 20120110392Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.Type: ApplicationFiled: January 6, 2012Publication date: May 3, 2012Inventors: Tse-Yu Yeh, Po-Yung Chang, Eric Hao
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Patent number: 8171240Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.Type: GrantFiled: January 6, 2012Date of Patent: May 1, 2012Assignee: Apple Inc.Inventors: Tse-Yu Yeh, Po-Yung Chang, Eric Hao
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Patent number: 8117404Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.Type: GrantFiled: August 10, 2005Date of Patent: February 14, 2012Assignee: Apple Inc.Inventors: Tse-Yu Yeh, Po-Yung Chang, Eric Hao
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Publication number: 20110238961Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Inventors: John Banning, Eric Hao, Brett Coon
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Patent number: 7984277Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: GrantFiled: February 2, 2010Date of Patent: July 19, 2011Inventors: John Banning, Eric Hao, Brett Coon
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Patent number: 7984274Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.Type: GrantFiled: June 18, 2009Date of Patent: July 19, 2011Assignee: Apple Inc.Inventors: Sudarshan Kadambi, Po-Yung Chang, Eric Hao
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Publication number: 20100138638Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: ApplicationFiled: February 2, 2010Publication date: June 3, 2010Inventors: John Banning, Eric Hao, Brett Coon
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Patent number: 7698539Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.Type: GrantFiled: September 26, 2003Date of Patent: April 13, 2010Inventors: John P. Banning, Eric Hao, Brett Coon
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Patent number: 7606997Abstract: A method and system for expanding an instruction set by decoding an instruction located at a particular address using one or more of those address bits in conjunction with the instruction word.Type: GrantFiled: July 18, 2003Date of Patent: October 20, 2009Inventors: Guillermo Rozas, Alexander Klaiber, Eric Hao
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Publication number: 20090254734Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.Type: ApplicationFiled: June 18, 2009Publication date: October 8, 2009Inventors: Sudarshan Kadambi, Po-Yung Chang, Eric Hao
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Patent number: 7568087Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.Type: GrantFiled: March 25, 2008Date of Patent: July 28, 2009Assignee: Apple Inc.Inventors: Sudarshan Kadambi, Po-Yung Chang, Eric Hao
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Publication number: 20080177988Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.Type: ApplicationFiled: March 25, 2008Publication date: July 24, 2008Inventors: Sudarshan Kadambi, Po-Yung Chang, Eric Hao
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Patent number: 7376817Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.Type: GrantFiled: August 10, 2005Date of Patent: May 20, 2008Assignee: P.A. Semi, Inc.Inventors: Sudarshan Kadambi, Po-Yung Chang, Eric Hao
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Publication number: 20070038847Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.Type: ApplicationFiled: August 10, 2005Publication date: February 15, 2007Applicant: P.A. Semi, Inc.Inventors: Tse-Yu Yeh, Po-Yung Chang, Eric Hao
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Publication number: 20070038846Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.Type: ApplicationFiled: August 10, 2005Publication date: February 15, 2007Applicant: P.A. Semi, Inc.Inventors: Sudarshan Kadambi, Po-Yung Chang, Eric Hao
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Patent number: 6640297Abstract: The speed of processing of a sequence of indirect branch instructions in a pipelined processor is increased by overlapping the latencies in the sequence of indirect branch instructions. The architecture of a digital processor is modified to include a link pipe system that allows the sequence of branch addresses required by the indirect branches to be written to a single location within the processor, and to be read from a single location in the processor. The link pipe system contains a plurality of registers (3, 5 & 7) for storage of respective branch target addresses. Each WRITE of a branch address is automatically directed (9) to individual registers within the link pipe system for storing the respective branch addresses; and each READ of a branch address is automatically directed (11) to the register containing the earliest WRITE of an address that was not previously read by the processor, whereby branch target addresses are retrieved on a “first in, first out” basis.Type: GrantFiled: June 19, 2000Date of Patent: October 28, 2003Assignee: Transmeta CorporationInventors: John Banning, Brett Coon, Eric Hao