Patents by Inventor Eric Hunt-Schroeder

Eric Hunt-Schroeder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11112811
    Abstract: Disclosed are embodiments of an integrated circuit (IC) chip that includes an on-chip parameter generation system. The system includes multiple parameter generators (e.g., voltage generators, current generators, capacitance generators, etc.) and an integrated calibration circuit. The calibration circuit is configured to automatically, sequentially, and repeatedly calibrate the parameter generators in order to minimize chip-to-chip variations in parameters supplied to other on-chip components under real world operating conditions throughout the life of the IC chip. In other words, the integrated calibration circuit effectively minimizes temperature-induced chip-to-chip variations, age-induced chip-to-chip variations, etc. in parameters generated by the on-chip parameter generators. Also disclosed herein are embodiments of an associated method.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: September 7, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Eric Hunt-Schroeder, Alexander J. Filmer
  • Publication number: 20210223809
    Abstract: Disclosed are embodiments of an integrated circuit (IC) chip that includes an on-chip parameter generation system. The system includes multiple parameter generators (e.g., voltage generators, current generators, capacitance generators, etc.) and an integrated calibration circuit. The calibration circuit is configured to automatically, sequentially, and repeatedly calibrate the parameter generators in order to minimize chip-to-chip variations in parameters supplied to other on-chip components under real world operating conditions throughout the life of the IC chip. In other words, the integrated calibration circuit effectively minimizes temperature-induced chip-to-chip variations, age-induced chip-to-chip variations, etc. in parameters generated by the on-chip parameter generators. Also disclosed herein are embodiments of an associated method.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Applicant: Marvell International Ltd.
    Inventors: Eric Hunt-Schroeder, Alexander J. Filmer
  • Patent number: 10673321
    Abstract: Methods produce IC devices that include a multiplexor that is electrically connected to a bandgap reference generator and a charge pump. The multiplexor receives voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator. The multiplexor outputs, to the charge pump, either: a retry signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are below a voltage threshold) or a pump signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are not below the voltage threshold). The pump signal causes the charge pump to output the voltage-boosted clock signal to the bandgap reference generator. The retry signal causes the charge pump to not output the voltage-boosted clock signal to the bandgap reference generator, and instead to precharge the charge pump.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Marvell Asia Pte., Ltd.
    Inventors: Eric Hunt-Schroeder, John A. Fifield, Dale E. Pontius
  • Patent number: 10446239
    Abstract: An array of memory cells in rows and columns with each column having a corresponding reference cell and a corresponding comparator. Each memory cell in a given row and given column is connected to a memory wordline for the row and to a memory bitline for the column. Each reference cell is connected to a reference wordline for the reference cells and to a reference bitline. Each comparator for a column has a current mirror with a reference section connected to the reference bitline for the reference cell for the column and a memory section connected to the memory bitline for the memory cells in the column. Each reference section has a current mirror node and all current mirror nodes in the array are connected to reduce mismatch and improve sensing accuracy. Voltages applied to the memory and reference wordlines are varied to provide accurate single-ended sensing, margin testing, etc.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Eric Hunt-Schroeder
  • Patent number: 10429434
    Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Eric Hunt-Schroeder, Mark D. Jacunski
  • Publication number: 20190265293
    Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Inventors: John A. Fifield, Eric Hunt-Schroeder, Mark D. Jacunski
  • Patent number: 10382049
    Abstract: Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by ½ DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by ½ DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDARIES INC.
    Inventors: Eric Hunt-Schroeder, John A. Fifield
  • Publication number: 20190165669
    Abstract: Methods produce IC devices that include a multiplexor that is electrically connected to a bandgap reference generator and a charge pump. The multiplexor receives voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator. The multiplexor outputs, to the charge pump, either: a retry signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are below a voltage threshold) or a pump signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are not below the voltage threshold). The pump signal causes the charge pump to output the voltage-boosted clock signal to the bandgap reference generator. The retry signal causes the charge pump to not output the voltage-boosted clock signal to the bandgap reference generator, and instead to precharge the charge pump.
    Type: Application
    Filed: November 27, 2017
    Publication date: May 30, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Eric Hunt-Schroeder, John A. Fifield, Dale E. Pontius
  • Patent number: 10192590
    Abstract: Differential voltage generators receive an initial target voltage, and provide the initial target voltage to a first offset element and a second offset element. The first offset element includes first transistors, and the second offset element includes second transistors. Each of the first transistors is capable of changing the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage. The second transistors are capable of removing a current generated by the first transistors, thereby causing an opposite current and leaving the initial target voltage unaffected on a second output. Each of the first transistors has a corresponding second transistor that produces the same current. A first output is capable of outputting the altered target voltage, and the second output is capable of outputting the initial target voltage.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Eric Hunt-Schroeder