Patents by Inventor Eric J. Crabill

Eric J. Crabill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7480786
    Abstract: Methods and cores using an existing processor implemented in a Programmable Logic Device (PLD) to emulate a target processor, where the existing and target processors support different instruction sets and conform to different bus interface protocols. A bus interface unit is coupled to an existing processor in a PLD. The bus interface unit is implemented using the programmable logic resources of the PLD, while the existing processor can be a dedicated processor or an existing “soft” processor. The bus interface unit acts as a peripheral device to translate bus transactions from the existing bus protocol (i.e., the bus protocol understood by the existing processor) to the target bus protocol. In addition, a stored emulation program emulates the target instruction set while executing instructions using the instruction set supported by the existing processor.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventor: Eric J. Crabill
  • Patent number: 6920551
    Abstract: A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath unit. The instruction processing unit further contains a configurable microcode unit and a non-configurable sequencing unit. The programmable integrated circuit can be programmed so that a microcode compatible with a target microprocessor is installed in the configurable microcode unit. The superset datapath unit is a superset of the datapath elements of all the target microprocessors.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: July 19, 2005
    Assignee: Xilinx, Inc.
    Inventor: Eric J. Crabill
  • Patent number: 6725364
    Abstract: A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath unit. The instruction processing unit further contains a configurable microcode unit and a non-configurable sequencing unit. The programmable integrated circuit can be programmed so that a microcode compatible with a target microprocessor is installed in the configurable microcode unit. The superset datapath unit is a superset of the datapath elements of all the target microprocessors.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: April 20, 2004
    Assignee: Xilinx, Inc.
    Inventor: Eric J. Crabill
  • Patent number: 6525557
    Abstract: A core for a register-based programmable logic device includes a register configured to provide a hidden identifier in response to a secret unlock operation. The identifier is inaccessible during normal operation of the core implementation. The unlock operation is selected to be an action or set of actions that would typically not be performed during normal use of the core implementation. The logic associated with providing the hidden identifier in response to the unlock operation is configured to not interfere with normal operation of the core implementation. Therefore, the presence of this source identification capability is transparent to regular users (and unauthorized copyists) of the core implementation. The availability of the secondary identifier can be limited in duration to minimize the chances of accidental, or even intentional, discovery.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: February 25, 2003
    Assignee: Xilinx, Inc.
    Inventors: James L. McManus, Eric J. Crabill, James L. Burnham
  • Patent number: 6292020
    Abstract: Described are programmable routing resources capable of distributing low-skew signals along more than one edge of a programmable logic device (PLD). The PLD includes groups of input/output blocks (IOBs) arranged along each edge. A programmable signal-distribution tree can be configured to send a shared, low-skew signal to IOBs along adjacent edges. These signals are conveyed via perpendicular conductive lines that run parallel to the respective edges. Each conductive line can be programmably connected to a source of the shared signal using a respective programmable-interconnect point located near the corner of the PLD defined by the two edges.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: September 18, 2001
    Assignee: Xilinx, Inc.
    Inventor: Eric J. Crabill