Patents by Inventor Eric J. DeHaemer

Eric J. DeHaemer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100005234
    Abstract: In one embodiment, the present invention includes a method for reading configuration information from a multi-function device (MFD), building a dependency tree of a functional dependency of functions performed by the MFD based on the configuration information, which indicates that the MFD is capable of performing at least one function dependent upon another function, and loading software associated with the functions in order based at least in part on the indicated functional dependency. Other embodiments are described and claimed.
    Type: Application
    Filed: June 30, 2008
    Publication date: January 7, 2010
    Inventors: Ilango S. Ganga, Manoj K. Wadekar, Eric J. DeHaemer
  • Patent number: 7552242
    Abstract: An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor and a switch. The switch may comprise one or more ports capable of being coupled to one or more segments external to the switch. The processor may be capable of issuing to the switch one or more commands indicating, at least in part, one or more protocols via which the one or more ports are to communicate and/or one or more forwarding characteristics of the switch. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: June 23, 2009
    Assignee: Intel Corporation
    Inventors: Eric J. DeHaemer, Deif N. Atallah
  • Patent number: 7480832
    Abstract: A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Suresh Chemudupati, Victor T. Lau, Bruno DiPlacido, Eric J. DeHaemer
  • Patent number: 7080164
    Abstract: Methods and apparatuses for programming identifications of a peripheral device are described herein. According to one embodiment, the exemplary method includes programming, based on predefined data, one or more fields of configuration registers of a peripheral device in response to a configuration cycle of a data processing system, the one or more fields of the configuration registers including at least one identification register for identifying the peripheral device. Other methods and apparatuses are also described.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: July 18, 2006
    Assignee: Intel Corporation
    Inventors: Paul A. Jacobs, Eric J. DeHaemer
  • Patent number: 6594722
    Abstract: A circuit is provided that includes a bridge circuit for connecting a first bus to a second bus. The bridge circuit also includes a first bus interface coupled to the first bus and is adapted to receive a plurality of transactions from the first bus. Each transaction has an address targeting the second bus and data the length of which defines a transaction size. A request data engine for issuing requests on a second bus is also provided. The request data engine is capable of assigning a unique encoded header to data streams. Control logic is provided that is adapted to store a first portion of a first transaction of the plurality of transactions in a memory coupled between the first bus and the second bus. Management logic is provided that is adapted to manage multiple out-of-order data streams wherein the data streams may remain outstanding to the bridge circuit. Additionally, a method is provided that includes capturing a data stream request header. Determining which data stream a request is mapped into.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventors: Theodore L. Willke, II, Eric J. DeHaemer