Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Abstract: A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.

Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Abstract: A method and a system for expressing results of a timing analysis of an integrated circuit (IC) chip design as relative values to drive efficient chip design closure include: using a computer, performing the timing analysis to compute timing results of the chip design across at least two design corners; applying corner specific normalization equations to the timing analysis results from each of the at least two corners to obtain normalized timing results; and using the timing results ordered and filtered by the normalized timing results of the IC chip design for the design closure prior to chip manufacture. The slacks are normalized to provide insight into the degree of difficulty of the required fixes for that slack across corners. Given multiple analyses, the slacks are fixed in a correct order across corners and paths, avoiding inefficient circuit solutions or cost greater design effort.

Abstract: A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.

Abstract: An approach for performing device-based random variability modeling in timing analysis of a digital integrated circuit having a gate-level design and a device-level custom design is described. In one embodiment, an algorithm is derived from results of simulating the operational behavior of a representative digital integrated circuit. A timing analysis is performed on the device-level custom design part of the digital integrated circuit to obtain device-level random variability sensitivity values. A gate-level characterization is performed on the gate-level design part of the digital integrated circuit to obtain logic gate random variability sensitivity values. A timing analysis is performed on the digital integrated circuit as a function of both the device-level random variability sensitivity values and the logic gate random variability sensitivity values.

Abstract: A method and multithreaded processor for dynamically reallocating prefetch registers upon the processor switching modes of operation. An execution unit may be coupled to a prefetch engine where the execution unit may be configured to receive prefetch instructions regarding prefetching data. The prefetch engine may comprise a plurality of prefetch registers. The execution unit may further be configured to load the plurality of prefetch registers with information regarding prefetching data obtained from the prefetch instructions. In a single thread mode of operation, the plurality of prefetch registers are allocated to be accessed by either a first or a second thread. In a multithread mode of operation, the plurality of prefetch registers are allocated to be accessed among the first and second threads.

Abstract: In a system with multiple execution units, instructions are queued to allow efficient dispatching. One load/store unit (LSU) may have a store instruction pending to a real address and a second LSU may have a load instruction pending to the same real address. An SMT system has an atomic store quad word (SQW) instruction with a data path that is only double wide and the SQW requires two cycles to complete. The SMT system requires a method to prevent between collisions in a store reorder queue (SRQ) STQ. The real address of a load word (LW) one thread is compared to the real addresses in the SRQ of the second thread. If the SQW with a real address matching the real address of the LW has not committed both of its double words, then the LW of the second thread is rejected.

Abstract: A method and multithreaded processor for dynamically reallocating prefetch registers upon the processor switching modes of operation. An execution unit may be coupled to a prefetch engine where the execution unit may be configured to receive prefetch instructions regarding prefetching data. The prefetch engine may comprise a plurality of prefetch registers. The execution unit may further be configured to load the plurality of prefetch registers with information regarding prefetching data obtained from the prefetch instructions. In a single thread mode of operation, the plurality of prefetch registers are allocated to be accessed by either a first or a second thread. In a multithread mode of operation, the plurality of prefetch registers are allocated to be accessed among the first and second threads.

Abstract: In a system with multiple execution units, instructions are queued to allow efficient dispatching. One load/store unit (LSU) may have a store instruction pending to a real address and a second LSU may have a load instruction pending to the same real address. An SMT system has an atomic store quad word (SQW) instruction with a data path that is only double wide and the SQW requires two cycles to complete. The SMT system requires a method to prevent between collisions in a store reorder queue (SRQ) STQ. The real address of a load word (LW) one thread is compared to the real addresses in the SRQ of the second thread. If the SQW with a real address matching the real address of the LW has not committed both of its double words, then the LW of the second thread is rejected.