Patents by Inventor Eric J. Hoekstra

Eric J. Hoekstra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190251652
    Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
    Type: Application
    Filed: January 18, 2019
    Publication date: August 15, 2019
    Applicant: Intel Corporation
    Inventors: Balaji Vernbu, Murali Rarnadoss, Guei-Yuan Lueh, Subramaniam M. Maiyuran, Abhishek R. Appu, Joydeep Ray, Altug Koker, James A. Valerio, Eric J. Hoekstra, Arthur D. Hunter, JR.
  • Publication number: 20190251655
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 15, 2019
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Patent number: 10269088
    Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, Abhishek R. Appu, Subramaniam M. Maiyuran, Eric J. Hoekstra, Prasoonkumar Surti, Balaji Vembu, Altug Koker
  • Patent number: 10262388
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Patent number: 10235736
    Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Murali Ramadoss, Guei-Yuan Lueh, Subramaniam M. Maiyuran, Abhishek R. Appu, Joydeep Ray, Altug Koker, James A. Valerio, Eric J. Hoekstra, Arthur D. Hunter, Jr.
  • Publication number: 20180308272
    Abstract: Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Inventors: Abhishek R. Appu, Prasoonkumar Surti, Srivallaba Mysore, Subhajit Dasgupta, Hiroshi Akiba, Eric J. Hoekstra, Linda L. Hurd, Travis T. Schluessler, Daren J. Schmidt
  • Publication number: 20180308450
    Abstract: Methods and apparatus relating to techniques for provision of color mapping for better compression ratio are described. In an embodiment, a plurality of bits are moved from all channels of a first Red Green Blue Alpha (RGBA) space to an alpha channel of a second RGBA space. The plurality of the bits are selected from higher order bits of the first RGBA space. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Eric J. Hoekstra, Subramaniam Maiyuran, Prasoonkumar Surti, Eric G. Liskay, Joydeep Ray, Michael J. Norris, Wenyin Fu, Altug Koker
  • Publication number: 20180308196
    Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Subramaniam M. Maiyuran, Eric J. Hoekstra, Prasoonkumar Surti, Balaji Vembu, Altug Koker
  • Publication number: 20180308197
    Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Murali Ramadoss, Guei-Yuan Lueh, Subramaniam M. Maiyuran, Abhishek R. Appu, Joydeep Ray, Altug Koker, James A. Valerio, Eric J. Hoekstra, Arthur D. Hunter, JR.
  • Publication number: 20180300840
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to render data from an application to be displayed on a display panel, and a memory to store the compressed final display surface writes. The processor is to compress final display surface writes of the data to be displayed on the display panel in a format to be displayed on the display to allow a display engine coupled to the display to stream the compressed final display surface writes to the display.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 18, 2018
    Inventors: Joydeep Ray, Prasoonkumar Surti, Abhishek R. Appu, Travis T. Schluessler, Linda L. Hurd, Eric J. Hoekstra
  • Publication number: 20180300238
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 18, 2018
    Inventors: Balaji Vembu, Altug Koker, Josh B. Mastronarde, Nikos Kaburlasos, Abhishek R. Appu, Sanjeev S. Jahagirdar, Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Pattabhiraman K, Kamal Sinha, Bhushan M. Borole, Wenyin Fu, Joydeep Ray, Prasoonkumar Surti, Eric J. Hoekstra, Travis T. Schluessler, Linda L. Hurd
  • Publication number: 20180300933
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 18, 2018
    Inventors: Devan Burke, Adam T. Lake, Jeffery S. Boles, John H. Feit, Karthik Vaidyanathan, Abhishek R. Appu, Joydeep Ray, Subramaniam Maiyuran, Altug Koker, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Eric J. Hoekstra, Gabor Liktor, Jonathan Kennedy, Slawomir Grajewski, Elmoustapha Ould-Ahmed-Vall
  • Publication number: 20180293695
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Publication number: 20180284868
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Eric J. Hoekstra, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy
  • Publication number: 20180285106
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu, Subramaniam Maiyuran, Prasoonkumar Surti, Guei-Yuan Lueh, David Puffer, Supratim Pal, Eric J. Hoekstra, Travis T. Schluessler, Linda L. Hurd
  • Publication number: 20180284873
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Eric J. Hoekstra, Kiran C. Veernapu, Prasoonkumar Surti, Vasanth Ranganathan, Kamal Sinha, Balaji Vembu, Eric J. Asperheim, Sanjeev S. Jahagirdar, Joydeep Ray
  • Publication number: 20160093069
    Abstract: An apparatus and method for pixel hashing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a lookup in a data structure indexed based on the X and Y coordinates of the pixel block, the lookup identifying an entry in the data structure corresponding to the X and Y coordinates of the pixel block; reading information from the entry identifying an execution cluster to process the pixel block; and executing the pixel block by the execution cluster.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Subramaniam MAIYURAN, Saurabh SHARMA, Eric J. HOEKSTRA, Juan FERNANDEZ
  • Patent number: 8258703
    Abstract: A trailer light adapter that is adapted to supply signals to operate the lights of a towed vehicle from modulated signals of a lighting circuit of a towing vehicle, includes at least one input that is adapted to receive a modulated signal from the lighting circuit of the towing vehicle and at least one output that is adapted to supply an output signal to operate a light of the towed vehicle. The adapter further includes a decoder that is adapted to decode a modulated signal and to provide a decoded signal indicative of a desired state of the light of the towed vehicle. The adapter further includes a power circuit that is responsive to the decoded signal and is adapted to supply the output signal to operate the light of the towed vehicle. The adapter may be responsive to a variable voltage modulated signal, a pulse-width modulated signal, or the like.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: September 4, 2012
    Inventor: Eric J. Hoekstra
  • Patent number: 8129909
    Abstract: A trailer light converter that is configured to operate lights of a towed vehicle from signals supplied from lighting circuits of a towing vehicle includes at least one input that is adapted to be connected with the lighting circuits of a towing vehicle and at least one output that is adapted to be connected with the lights of a towed vehicle. At least one switch is provided that is responsive to a signal applied to the at least one input to supply electrical power to the at least one output to illuminate at least one light of the towed vehicle. The at least one switch includes a switching transistor and an overload protector. The at least one switch is responsive to the signal applied to the at least one input to change to a low impedance state to supply power to the at least one output. The overload protector is responsive to an overload condition on the at least one output to turn the at least one switch to a high impedance state to remove power from the least one output.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: March 6, 2012
    Inventor: Eric J. Hoekstra
  • Patent number: 8001696
    Abstract: A calibration method for calibrating a compass system suitable for use in a vehicle includes sampling data points of a magnetic field with a magneto-responsive sensor and processing output signals of the sensor via compass circuitry. The compass circuitry includes an analog-to-digital converter for converting analog signals of the sensor to digital signals and a digital-to-analog converter for converting digital signals to analog signals that are supplied to the sensor for adjusting the sensor. The output signals of the sensor are adjusted to be within an operable range of an analog-to-digital converter via an initial calibration mode. After completion of the initial calibration mode, output signals of the sensor are processed to determine when the output signals are outside a range of the analog-to-digital converter. An output of a digital-to-analog converter is adjusted to reposition the output signals of the sensor to be within the range of the analog-to-digital converter.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: August 23, 2011
    Assignee: Donnelly Corporation
    Inventors: Kenneth L. Schierbeek, Eric J. Hoekstra, Rodney K. Blank, Merdad Veiseh, Gregory H. DeVette, Kenneth Schofield